JPS6486372A - Data reproducing device - Google Patents

Data reproducing device

Info

Publication number
JPS6486372A
JPS6486372A JP62244836A JP24483687A JPS6486372A JP S6486372 A JPS6486372 A JP S6486372A JP 62244836 A JP62244836 A JP 62244836A JP 24483687 A JP24483687 A JP 24483687A JP S6486372 A JPS6486372 A JP S6486372A
Authority
JP
Japan
Prior art keywords
error rate
clock
minimize
bit error
recovery circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62244836A
Other languages
Japanese (ja)
Inventor
Noboru Murabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62244836A priority Critical patent/JPS6486372A/en
Publication of JPS6486372A publication Critical patent/JPS6486372A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Television Signal Processing For Recording (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To minimize the bit error rate even when the recording modulation system with different recording density is used by controlling the clock frequency of a clock recovery circuit minimizing the it error rate of a demodulated data. CONSTITUTION:A frequency of a reference signal of a voltage controlled oscillation circuit 13 and a time constant of a low pass filter circuit 14 are controlled so as to minimize the bit error rate included in the demodulated data DT to obtain a recovered clock signal CK10 in a clock recovery circuit 11. Thus, the clock of the clock recovery circuit 11 is controlled variably as a whole to obtain a recovered clock signal CK10 to minimize the bit error rate and the recovered clock signal corresponding to the recording modulation system with different recording density is obtained.
JP62244836A 1987-09-28 1987-09-28 Data reproducing device Pending JPS6486372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62244836A JPS6486372A (en) 1987-09-28 1987-09-28 Data reproducing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62244836A JPS6486372A (en) 1987-09-28 1987-09-28 Data reproducing device

Publications (1)

Publication Number Publication Date
JPS6486372A true JPS6486372A (en) 1989-03-31

Family

ID=17124687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62244836A Pending JPS6486372A (en) 1987-09-28 1987-09-28 Data reproducing device

Country Status (1)

Country Link
JP (1) JPS6486372A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0554310A (en) * 1990-05-31 1993-03-05 Samsung Electron Co Ltd Digital signal detector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0554310A (en) * 1990-05-31 1993-03-05 Samsung Electron Co Ltd Digital signal detector

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