JPS6486254A - Disk cache device - Google Patents

Disk cache device

Info

Publication number
JPS6486254A
JPS6486254A JP62244534A JP24453487A JPS6486254A JP S6486254 A JPS6486254 A JP S6486254A JP 62244534 A JP62244534 A JP 62244534A JP 24453487 A JP24453487 A JP 24453487A JP S6486254 A JPS6486254 A JP S6486254A
Authority
JP
Japan
Prior art keywords
data
mpu
host processor
resetting
undefined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62244534A
Other languages
Japanese (ja)
Other versions
JPH0630076B2 (en
Inventor
Mitsujirou Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62244534A priority Critical patent/JPH0630076B2/en
Publication of JPS6486254A publication Critical patent/JPS6486254A/en
Publication of JPH0630076B2 publication Critical patent/JPH0630076B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To improve reliability by setting a data undefined flag added to writing data when a resetting instruction is made from a central processing unit while a storing-in action is executed. CONSTITUTION:A microprocessor MPU 1 latches the resetting instruction from a host processor 30 to a resetting latch 3. When the resetting latch 3 is not set until data transfer from the host processor 30 is completed, the MPU 1 resets the data undefined flag, and when the resetting latch 3 is set until then, the MPU 1 sets the data undefined flag. Thereafter, for a searching and reading instruction from the host processor 30, the MPU 1 investigates the data undefined flag in a designated field, and when the data undefined flag is set, the MPU 1 informs the host processor 30 that the data of an accessed field are undefined.
JP62244534A 1987-09-28 1987-09-28 Disk cache device Expired - Lifetime JPH0630076B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62244534A JPH0630076B2 (en) 1987-09-28 1987-09-28 Disk cache device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62244534A JPH0630076B2 (en) 1987-09-28 1987-09-28 Disk cache device

Publications (2)

Publication Number Publication Date
JPS6486254A true JPS6486254A (en) 1989-03-30
JPH0630076B2 JPH0630076B2 (en) 1994-04-20

Family

ID=17120126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62244534A Expired - Lifetime JPH0630076B2 (en) 1987-09-28 1987-09-28 Disk cache device

Country Status (1)

Country Link
JP (1) JPH0630076B2 (en)

Also Published As

Publication number Publication date
JPH0630076B2 (en) 1994-04-20

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