JPS648587A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS648587A
JPS648587A JP62162319A JP16231987A JPS648587A JP S648587 A JPS648587 A JP S648587A JP 62162319 A JP62162319 A JP 62162319A JP 16231987 A JP16231987 A JP 16231987A JP S648587 A JPS648587 A JP S648587A
Authority
JP
Japan
Prior art keywords
split
memory array
xll
mal
word lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62162319A
Other languages
Japanese (ja)
Inventor
Katsutaka Kimura
Jun Eto
Katsuhiro Shimohigashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62162319A priority Critical patent/JPS648587A/en
Publication of JPS648587A publication Critical patent/JPS648587A/en
Pending legal-status Critical Current

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  • Dram (AREA)

Abstract

PURPOSE:To prevent malfunction by providing a latch circuit decentralizingly on the way of a signal wire to reduce the fluctuation of the potential induced via parasitic capacitance. CONSTITUTION:A memory array MA is split into plural memory arrays MA1-MAl and latch circuits XL1-XLl of word lines W1, W2 are arranged among the split memory arrays MA1-MAl. The words W1, W2 in the split memory array MA are selected by the same X decoder XD. Moreover, the word lines in the memory array are connected to each other in the location arranged with the latch circuits XL1-XLl. Thus, the potential fluctuation of the signal wire is suppressed to prevent malfunction via the parasitic capacitance.
JP62162319A 1987-07-01 1987-07-01 Semiconductor device Pending JPS648587A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62162319A JPS648587A (en) 1987-07-01 1987-07-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62162319A JPS648587A (en) 1987-07-01 1987-07-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS648587A true JPS648587A (en) 1989-01-12

Family

ID=15752270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62162319A Pending JPS648587A (en) 1987-07-01 1987-07-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS648587A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001167577A (en) * 1999-10-29 2001-06-22 Infineon Technologies Ag Integrated memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001167577A (en) * 1999-10-29 2001-06-22 Infineon Technologies Ag Integrated memory

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