JPS6484915A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6484915A
JPS6484915A JP62241064A JP24106487A JPS6484915A JP S6484915 A JPS6484915 A JP S6484915A JP 62241064 A JP62241064 A JP 62241064A JP 24106487 A JP24106487 A JP 24106487A JP S6484915 A JPS6484915 A JP S6484915A
Authority
JP
Japan
Prior art keywords
ground level
signal
usual
energized state
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62241064A
Other languages
Japanese (ja)
Inventor
Yukinobu Adachi
Kenji Tomigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62241064A priority Critical patent/JPS6484915A/en
Publication of JPS6484915A publication Critical patent/JPS6484915A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To equalize the transfer characteristic with that in a usual time even if a ground level rises by connecting in parallel a second transistor of a low threshold level to a first transistor of an inverter, and inputting an output signal of an input control circuit to its gate. CONSTITUTION:When a ground level exceeds a prescribed level, H being a signal ISC, and L being a signal ISC' are applied from the outside to the respective gates of N-type transistors Tr6, 7, and the Tr6 and the Tr7 go to a energized state and a cut-off state, respectively. As a result, from this input control circuit 5, an inputted input signal VIN is outputted as it is. Accordingly, the signal VIN is applied not only to gates of P-type and N-type Trs1, 2 in the same way as usual, but also to a gate of Tr4 through the circuit 5, therefore, even if the Tr2 does not go to an energized state due to rise of the ground level, when a voltage of the signal VIN is higher than a threshold voltage of the Tr4, the Tr4 goes to an energized state. As a result, the transfer characteristic goes to almost the same as the case when the ground level is usual.
JP62241064A 1987-09-26 1987-09-26 Semiconductor device Pending JPS6484915A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62241064A JPS6484915A (en) 1987-09-26 1987-09-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62241064A JPS6484915A (en) 1987-09-26 1987-09-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6484915A true JPS6484915A (en) 1989-03-30

Family

ID=17068761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62241064A Pending JPS6484915A (en) 1987-09-26 1987-09-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6484915A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010192901A (en) * 2009-02-18 2010-09-02 Samsung Electronics Co Ltd Sram using carbon nanotube thin film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010192901A (en) * 2009-02-18 2010-09-02 Samsung Electronics Co Ltd Sram using carbon nanotube thin film

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