JPS6482247A - State setting circuit - Google Patents
State setting circuitInfo
- Publication number
- JPS6482247A JPS6482247A JP24214887A JP24214887A JPS6482247A JP S6482247 A JPS6482247 A JP S6482247A JP 24214887 A JP24214887 A JP 24214887A JP 24214887 A JP24214887 A JP 24214887A JP S6482247 A JPS6482247 A JP S6482247A
- Authority
- JP
- Japan
- Prior art keywords
- port
- output
- terminal
- inverter
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To increase the number of settable states by providing a one-bit output port connected to a microprocessor by a bus and an inverter and an N-bit input port or the like which are connected to the output of said output port. CONSTITUTION:A microprocessor 4a is controlled by a program to read in an input port 3 after setting arbitrary data to an output port 1 through a bus 4, and the output of an inverter 2 goes to logical '1' when a terminal 5 of the port is set to logical '0'. At such a time, 0110 is given to respective terminals of the port in order from a terminal 9 of the most significant bit, and the processor 4a reads in input state 0110 of the port 3. When the output of the terminal 5 of the port 1 is set to '1', the output of the inverter 2 goes to 0, and 0101 is given to respective terminals of the port 3 in order from the terminal 9, and the processor 4a reads in input state 0101 of the port 3. In the program which the processor 4a executes, exclusive OR between 0110 and 0101 is operated to obtain 0011. Thus, the number of settable states is increased.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24214887A JPS6482247A (en) | 1987-09-25 | 1987-09-25 | State setting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24214887A JPS6482247A (en) | 1987-09-25 | 1987-09-25 | State setting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6482247A true JPS6482247A (en) | 1989-03-28 |
Family
ID=17085033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24214887A Pending JPS6482247A (en) | 1987-09-25 | 1987-09-25 | State setting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6482247A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5749488A (en) * | 1995-10-02 | 1998-05-12 | Reynolds Metals Company | Can end with recessed center panel formed downwardly from coin |
-
1987
- 1987-09-25 JP JP24214887A patent/JPS6482247A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5749488A (en) * | 1995-10-02 | 1998-05-12 | Reynolds Metals Company | Can end with recessed center panel formed downwardly from coin |
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