JPS6481004A - Pc program display system - Google Patents

Pc program display system

Info

Publication number
JPS6481004A
JPS6481004A JP62238128A JP23812887A JPS6481004A JP S6481004 A JPS6481004 A JP S6481004A JP 62238128 A JP62238128 A JP 62238128A JP 23812887 A JP23812887 A JP 23812887A JP S6481004 A JPS6481004 A JP S6481004A
Authority
JP
Japan
Prior art keywords
sequence program
map
directory
program
memory area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62238128A
Other languages
Japanese (ja)
Inventor
Kunio Tanaka
Hirosuke Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP62238128A priority Critical patent/JPS6481004A/en
Priority to PCT/JP1988/000940 priority patent/WO1989003068A1/en
Publication of JPS6481004A publication Critical patent/JPS6481004A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/058—Safety, monitoring

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)
  • Stored Programmes (AREA)
  • Testing And Monitoring For Control Systems (AREA)

Abstract

PURPOSE:To understand a memory map at a glance by providing a directory for each sequence program and displaying the memory area of each sequence program in the form of a map based on said directory. CONSTITUTION:A program controller contains directories for each sequence program. The contents of the directory are rewritten every time the corresponding sequence program is changed. If an instruction is received for display of the sequence program, the memory area of the corresponding sequence program is calculated by reference to the relevant directory. Thus the memory area of the sequence program is shown on a display screen in the form of a map. As a result, the program areas 15, 16, 19 and 20 and the data areas 12-14 are displayed in the map forms in accordance with the number of working bytes of said areas. Thus it is possible to understand a memory map at a glance.
JP62238128A 1987-09-22 1987-09-22 Pc program display system Pending JPS6481004A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62238128A JPS6481004A (en) 1987-09-22 1987-09-22 Pc program display system
PCT/JP1988/000940 WO1989003068A1 (en) 1987-09-22 1988-09-14 Method of displaying pc program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62238128A JPS6481004A (en) 1987-09-22 1987-09-22 Pc program display system

Publications (1)

Publication Number Publication Date
JPS6481004A true JPS6481004A (en) 1989-03-27

Family

ID=17025598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62238128A Pending JPS6481004A (en) 1987-09-22 1987-09-22 Pc program display system

Country Status (2)

Country Link
JP (1) JPS6481004A (en)
WO (1) WO1989003068A1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065337A (en) * 1983-09-20 1985-04-15 Fuji Facom Corp Output system for memory distribution pattern

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61118805A (en) * 1984-11-15 1986-06-06 Fuji Electric Co Ltd Programming device
JPS62152005A (en) * 1985-12-25 1987-07-07 Fanuc Ltd Generating method for sequence program

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065337A (en) * 1983-09-20 1985-04-15 Fuji Facom Corp Output system for memory distribution pattern

Also Published As

Publication number Publication date
WO1989003068A1 (en) 1989-04-06

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