JPS6477943A - Substrate for mounting electronic component - Google Patents

Substrate for mounting electronic component

Info

Publication number
JPS6477943A
JPS6477943A JP23572987A JP23572987A JPS6477943A JP S6477943 A JPS6477943 A JP S6477943A JP 23572987 A JP23572987 A JP 23572987A JP 23572987 A JP23572987 A JP 23572987A JP S6477943 A JPS6477943 A JP S6477943A
Authority
JP
Japan
Prior art keywords
pair
sides
electronic component
mutually
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23572987A
Other languages
Japanese (ja)
Other versions
JP2534515B2 (en
Inventor
Nobumasa Goto
Teruo Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP23572987A priority Critical patent/JP2534515B2/en
Publication of JPS6477943A publication Critical patent/JPS6477943A/en
Application granted granted Critical
Publication of JP2534515B2 publication Critical patent/JP2534515B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

Abstract

PURPOSE:To conduct mechanical recognition sufficiently positively by forming a triangular alignment pattern, two pairs of corresponding both sides of which are mutually parallel while the directions of movement of the positions of these sides by etching, plating, etc., are respectively opposite. CONSTITUTION:A substrate 10 for loading an electronic component has an electronic component loading section 12 shaped onto an insulating substrate 11 and a plurality of conductor patterns 13. A pair of alignment patterns 20 are formed between a pair of the conductor patterns 13 so as to be mutually opposed. At least two pairs of corresponding both sides 21 mutually run parallel in a pair of mutually opposite triangular alignment patterns 20, and the directions of movement of the positions of corresponding both sides 21 by etching, plating, etc., are opposed. Two pairs or more of a pair of these triangular alignment patterns 20 are shaped.
JP23572987A 1987-09-18 1987-09-18 Electronic component mounting board Expired - Lifetime JP2534515B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23572987A JP2534515B2 (en) 1987-09-18 1987-09-18 Electronic component mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23572987A JP2534515B2 (en) 1987-09-18 1987-09-18 Electronic component mounting board

Publications (2)

Publication Number Publication Date
JPS6477943A true JPS6477943A (en) 1989-03-23
JP2534515B2 JP2534515B2 (en) 1996-09-18

Family

ID=16990366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23572987A Expired - Lifetime JP2534515B2 (en) 1987-09-18 1987-09-18 Electronic component mounting board

Country Status (1)

Country Link
JP (1) JP2534515B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128990A (en) * 2005-11-02 2007-05-24 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128990A (en) * 2005-11-02 2007-05-24 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JP2534515B2 (en) 1996-09-18

Similar Documents

Publication Publication Date Title
BR8402803A (en) METALIZATION PROCESS FOR CERAMIC SUBSTRATES; METHOD FOR OBTAINING A PRINTED CIRCUIT ON CERAMIC SUBSTRATE; PROCESS FOR THE PRODUCTION OF A METALLIZED CONDUCTOR PATTERN, CERAMIC ITEM, METHOD FOR ADHESING TWO CERAMIC ITEMS
DE3373256D1 (en) Process for manufacturing printed circuits with metallic conductor patterns embedded in the isolating substrate
JPS53147772A (en) Manufacture of pressure-conductive elastomer
CA2030826A1 (en) Composite circuit board with thick embedded conductor and method of manufacturing the same
EP0265629A3 (en) Printed circuit card fabrication process with nickel overplate
KR910001499A (en) Electronic watch
JPS6477943A (en) Substrate for mounting electronic component
EP0737025A4 (en) Printed wiring board
GB8823537D0 (en) Circuit board manufacture
ES8309032A1 (en) Method of butt-connecting printed circuit boards
JPS54134902A (en) Chassis structure of electronic apparatus
JPS6464285A (en) Printed board
JPS6482595A (en) Printed wiring board
JPS5273395A (en) Connector
JPS5371862A (en) Circuit block and liquid crystal panel of electronic watch
JPS6484224A (en) Electrode forming method
FR2566612B1 (en) PROCESS FOR THE MANUFACTURE OF PRINTED CIRCUIT BOARDS, AND WAFER THUS OBTAINED
JPS6428891A (en) Multi-layer printed circuit board
JPS647528A (en) Manufacture of semiconductor device
JPS649686A (en) Mounting structure of circuit board
JPS6428830A (en) Substrate for mounting semiconductor
JPS6454682A (en) Connector
ES2006071A6 (en) Cladding of substrates with thick metal circuit patterns
SE9203533D0 (en) DEVICE FOR COOLING DISC-POWER ELECTRONIC ELEMENTS AS FOR DISC-POWER ELECTRONIC CONTROL PROVIDED TO BE INSTALLED IN SUCH COOLING DEVICE
JPS6490587A (en) Fpc for fine wiring

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080627

Year of fee payment: 12