JPS647713A - Memory device - Google Patents

Memory device

Info

Publication number
JPS647713A
JPS647713A JP63031600A JP3160088A JPS647713A JP S647713 A JPS647713 A JP S647713A JP 63031600 A JP63031600 A JP 63031600A JP 3160088 A JP3160088 A JP 3160088A JP S647713 A JPS647713 A JP S647713A
Authority
JP
Japan
Prior art keywords
output
signal
trouble
input signal
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63031600A
Other languages
Japanese (ja)
Inventor
Koichi Yomogihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Signal Co Ltd
Original Assignee
Nippon Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority to JP63031600A priority Critical patent/JPS647713A/en
Publication of JPS647713A publication Critical patent/JPS647713A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
    • H03K21/403—Arrangements for storing the counting state in case of power supply interruption

Landscapes

  • Train Traffic Observation, Control, And Security (AREA)

Abstract

PURPOSE:To specify an output at the time of trouble and to make it into a safe side trouble by AND-processing a bias signal and an input signal, feeding back an output and executing self-holding. CONSTITUTION:Memory circuit is LS1-LS4 provided in parallel to a memory device MY are formed by an AND circuit, the input signal of a setting signal added to respective terminals (a) and (b) and a bias signal RS are AND- processed and the output similar to the setting signal is generated. The output signal is fed back to the terminal (a), and the input signal is self-held and stored. By such constitution, when a bias signal goes to zero V, a feedback loop, etc., fail, the circuits LS1-LS4 are reset, an output is fixed to '0', the trouble is made into a safe side trouble and a satisfactory fail safe action is executed.
JP63031600A 1988-02-13 1988-02-13 Memory device Pending JPS647713A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63031600A JPS647713A (en) 1988-02-13 1988-02-13 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63031600A JPS647713A (en) 1988-02-13 1988-02-13 Memory device

Publications (1)

Publication Number Publication Date
JPS647713A true JPS647713A (en) 1989-01-11

Family

ID=12335691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63031600A Pending JPS647713A (en) 1988-02-13 1988-02-13 Memory device

Country Status (1)

Country Link
JP (1) JPS647713A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018167715A (en) * 2017-03-30 2018-11-01 大同信号株式会社 Axle counter
US10471511B2 (en) 2013-11-25 2019-11-12 United Technologies Corporation Method of manufacturing a hybrid cylindrical structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177054A (en) * 1974-12-27 1976-07-03 Hitachi Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177054A (en) * 1974-12-27 1976-07-03 Hitachi Ltd

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10471511B2 (en) 2013-11-25 2019-11-12 United Technologies Corporation Method of manufacturing a hybrid cylindrical structure
JP2018167715A (en) * 2017-03-30 2018-11-01 大同信号株式会社 Axle counter

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