JPS6476496A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS6476496A
JPS6476496A JP62231906A JP23190687A JPS6476496A JP S6476496 A JPS6476496 A JP S6476496A JP 62231906 A JP62231906 A JP 62231906A JP 23190687 A JP23190687 A JP 23190687A JP S6476496 A JPS6476496 A JP S6476496A
Authority
JP
Japan
Prior art keywords
sense amplifier
memory cell
word line
logical address
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62231906A
Other languages
Japanese (ja)
Other versions
JP2743997B2 (en
Inventor
Yoji Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62231906A priority Critical patent/JP2743997B2/en
Priority to KR1019880011975A priority patent/KR920005121B1/en
Publication of JPS6476496A publication Critical patent/JPS6476496A/en
Priority to US08/007,012 priority patent/US5274596A/en
Application granted granted Critical
Publication of JP2743997B2 publication Critical patent/JP2743997B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To attain a high speed access by distributing a word line to be selected to a different memory cell array block with a row address to be closed in a logical address plain, rising the adjacent word line and activating a sense amplifier. CONSTITUTION:For the plural numbers of memory blocks 11-1n of a memory cell array, a 2m-numbers of blocks to be selected with the low order row address of a lowest (m) bit, for example, are obtained. The word line to be selected with an adjacent row address on the logical address plain is arranged to a different block and when the inside of a logical address (i) line is accessed, simultaneously, the word lines of (i+ or -1), (i+ or -2)...(i+ or -j) rise. Further, the sense amplifier of the block, to which those word lines belong, is also activated and the information of the selected memory cell are latched into the sense amplifier. Thus, the high speed access can be executed not only in a column direction but also in a row direction and an inclining direction.
JP62231906A 1987-09-16 1987-09-16 Semiconductor storage device Expired - Lifetime JP2743997B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62231906A JP2743997B2 (en) 1987-09-16 1987-09-16 Semiconductor storage device
KR1019880011975A KR920005121B1 (en) 1987-09-16 1988-09-16 Semiconductor memory device
US08/007,012 US5274596A (en) 1987-09-16 1993-01-21 Dynamic semiconductor memory device having simultaneous operation of adjacent blocks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62231906A JP2743997B2 (en) 1987-09-16 1987-09-16 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS6476496A true JPS6476496A (en) 1989-03-22
JP2743997B2 JP2743997B2 (en) 1998-04-28

Family

ID=16930904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62231906A Expired - Lifetime JP2743997B2 (en) 1987-09-16 1987-09-16 Semiconductor storage device

Country Status (2)

Country Link
JP (1) JP2743997B2 (en)
KR (1) KR920005121B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238323A (en) * 2008-03-27 2009-10-15 Fujitsu Microelectronics Ltd Semiconductor memory device, image processing system and image processing method
JP2015053094A (en) * 2013-09-06 2015-03-19 株式会社東芝 Semiconductor storage device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60260086A (en) * 1984-06-07 1985-12-23 工業技術院長 Memory circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60260086A (en) * 1984-06-07 1985-12-23 工業技術院長 Memory circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238323A (en) * 2008-03-27 2009-10-15 Fujitsu Microelectronics Ltd Semiconductor memory device, image processing system and image processing method
JP2015053094A (en) * 2013-09-06 2015-03-19 株式会社東芝 Semiconductor storage device

Also Published As

Publication number Publication date
JP2743997B2 (en) 1998-04-28
KR920005121B1 (en) 1992-06-26
KR890005738A (en) 1989-05-16

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