JPS647591B2 - - Google Patents
Info
- Publication number
- JPS647591B2 JPS647591B2 JP55111130A JP11113080A JPS647591B2 JP S647591 B2 JPS647591 B2 JP S647591B2 JP 55111130 A JP55111130 A JP 55111130A JP 11113080 A JP11113080 A JP 11113080A JP S647591 B2 JPS647591 B2 JP S647591B2
- Authority
- JP
- Japan
- Prior art keywords
- recording
- voltage
- recording element
- control circuit
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 230000020169 heat generation Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000001454 recorded image Methods 0.000 description 2
- 238000003079 width control Methods 0.000 description 2
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
- B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
- B41J2/35—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads providing current or voltage to the thermal head
- B41J2/355—Control circuits for heating-element selection
- B41J2/36—Print density control
Landscapes
- Particle Formation And Scattering Control In Inkjet Printers (AREA)
- Electronic Switches (AREA)
- Facsimile Heads (AREA)
Description
【発明の詳細な説明】
本発明は、少なくとも発熱体を有する記録要素
を用いて印字記録する記録装置の記録要素制御回
路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording element control circuit for a recording apparatus that performs printing using a recording element having at least a heating element.
この種記録装置、例えば、サーマルヘツド記録
装置やサーマルインクジエツト記録装置において
は、高速度な記録を実現するため、印字紙等の記
録媒体の幅に見合つた数、すなわち、所要画素数
の記録要素を配置している。したがつて、非常に
多数の記録要素が必要となる。例えば、８画素を
１mmとしてA4版記録用紙を用い、主走査を用紙
の短い方向にとつた場合には、1700個程度の記録
要素が必要となる。 In this type of recording device, for example, a thermal head recording device or a thermal inkjet recording device, in order to achieve high-speed recording, the number of recording elements corresponding to the width of the recording medium such as printing paper, that is, the required number of pixels, is used. are placed. Therefore, a very large number of recording elements is required. For example, if A4 size recording paper is used with 8 pixels of 1 mm and main scanning is performed in the short direction of the paper, approximately 1700 recording elements are required.
このような多数の記録要素を個別に駆動するた
めに、各記録要素を制御する駆動素子と各記録要
素とを個別に配線することは、配線が複雑となり
好ましくない。そこで、従来、第１図あるいは第
２図に示すようなダイナミツク駆動回路により複
数の記録要素を制御している。 In order to drive such a large number of recording elements individually, it is not preferable to individually wire the drive element that controls each recording element and each recording element because the wiring becomes complicated. Therefore, conventionally, a plurality of recording elements are controlled by a dynamic drive circuit as shown in FIG. 1 or 2.
第１図において、Ｇ１〜Ｇ５６は、少なくとも
発熱体を持つ記録要素Ｈ１〜Ｈ３２をそれぞれ有
する記録要素群であり、本例では56の要素群がそ
れぞれ32本の記録要素を有しているものとする。
DIは記録要素Ｈ１〜Ｈ３２にそれぞれ接続され
ている記録要素分離用のダイオードであり、HA
は要素群Ｇ１〜Ｇ５６およびダイオードDIを含
んだ記録要素アレーである。各群Ｇ１〜Ｇ５６の
各要素Ｈ１〜Ｈ３２のいずれを発熱させるかは、
次のようにして行う。すなわち、信号供給源SS
から各群Ｇ１〜Ｇ５６のいずれかに、群選択駆動
信号として駆動電圧SG１〜SG５６を時分割によ
り順次に供給して、所望の群に所定の電圧を供給
するとともに、信号供給源SSから各要素Ｈ１〜
Ｈ３２のいずれかに、駆動信号SH１〜SH３２を
各群毎の時分割により順次に供給する。これによ
り、所望の要素群Giの所望の要素Hiを発熱させ
て印字紙等に文字等が記録される。ここで、信号
供給源SSついて説明する。 In FIG. 1, G1 to G56 are recording element groups each having recording elements H1 to H32 each having at least a heating element, and in this example, each of the 56 element groups has 32 recording elements. do.
DI is a recording element separation diode connected to each of the recording elements H1 to H32, and HA
is a recording element array including element groups G1 to G56 and diodes DI. Which of the elements H1 to H32 of each group G1 to G56 generates heat is determined by
Do it as follows. That is, the signal source SS
Drive voltages SG1 to SG56 are sequentially supplied as group selection drive signals to any of the groups G1 to G56 in a time-division manner, and a predetermined voltage is supplied to the desired group, and each element is controlled from the signal supply source SS. H1～
The drive signals SH1 to SH32 are sequentially supplied to one of the drive signals SH1 to SH32 by time division for each group. As a result, a desired element Hi of a desired element group Gi is made to generate heat, and a character or the like is recorded on printing paper or the like. Here, the signal supply source SS will be explained.
まず、予め選択された所望の要素駆動信号SHi
がラツチ回路Ｌ１に格納される。また、予め選択
された２進数６ビツト（26＝64通り）の群選択信
号SL１〜SL６がラツチ回路Ｌ２に格納される。
ラツチ回路Ｌ２に格納された群選択信号SL１〜
SL６はデコーダDECでデコードされ、所定電圧
値の群選択駆動信号SGiが得られる。群選択信号
SG１〜SG５６は時分割により順次取出されて、
所望の要素群Giを選択して電圧を供給する。な
お、群選択信号SG１〜SG５６は、パルス幅制御
回路PCにより、所定の時間だけ立上る。また、
各信号SH１〜SH３２，SG１〜SG５６は、それ
ぞれスイツチング素子群DS１，DS２を介して要
素群Ｇ１〜Ｇ５６に供給される。 First, a preselected desired element drive signal SHi
is stored in the latch circuit L1. Further, group selection signals SL1 to SL6 of preselected binary 6-bit numbers (2 6 =64 ways) are stored in the latch circuit L2.
Group selection signal SL1~ stored in latch circuit L2
SL6 is decoded by a decoder DEC, and a group selection drive signal SGi of a predetermined voltage value is obtained. Group selection signal
SG1 to SG56 are taken out sequentially by time division,
A desired element group Gi is selected and voltage is supplied. Note that the group selection signals SG1 to SG56 rise only for a predetermined time by the pulse width control circuit PC. Also,
The signals SH1 to SH32 and SG1 to SG56 are supplied to the element groups G1 to G56 via switching element groups DS1 and DS2, respectively.
第２図は、本願人が先に提案した記録要素制御
回路であり、要素分離用のダイオードDIに代え、
トランジスタTR（例えば、バイポーラトランジ
スタ）を用いると共に、記録要素Ｈ１〜Ｈ３２に
電源PWにより、常時所定の電圧を供給するよう
にしたものである。すなわち、信号供給源SSか
ら時分割により取出した所望の群選択信号SGi
（第１図に示した駆動電圧としての信号と異なり、
トランジスタTRのオン・オフを制御するための
信号）を、各要素Ｈ１〜Ｈ３２に接続したトラン
ジスタTRのベースに順次供給する。一方、同様
にして信号供給源SSら取出した駆動信号SHiを
トランジスタTRのエミツタに順次供給する。こ
れら各信号SGi，SHiにより、所望の要素群Giの
所望の記録要素Hiを順次発熱させて、印字紙等
に文字等が記録される。 Figure 2 shows the recording element control circuit proposed earlier by the applicant, in which, instead of a diode DI for element separation,
A transistor TR (for example, a bipolar transistor) is used, and a predetermined voltage is always supplied to the recording elements H1 to H32 by a power source PW. That is, the desired group selection signal SGi extracted by time division from the signal source SS
(Unlike the signal as the drive voltage shown in Figure 1,
A signal for controlling on/off of the transistor TR is sequentially supplied to the base of the transistor TR connected to each element H1 to H32. On the other hand, drive signals SHi taken out from the signal supply source SS in the same manner are sequentially supplied to the emitters of the transistors TR. These signals SGi and SHi sequentially cause the desired recording elements Hi of the desired element group Gi to generate heat, thereby recording characters and the like on printing paper or the like.
しかしながら、このように多数の記録要素に同
一の電力を供給して記録すると、記録要素間ある
いは記録要素群間における各種印字特性（サーマ
ルヘツド記録装置においては発熱特性、サーマル
インクジエツト記録装置においては発熱特性を含
んだ吐出特性）のばらつきに起因して、記録濃度
にむらができてしまう。ここで、要素群内におけ
る各要素のばらつきによる濃度のむらよりも、各
要素群間のばらつきによる濃度のむらがより問題
となる。 However, when recording by supplying the same power to a large number of recording elements, various printing characteristics (heat generation characteristics in thermal head recording devices, heat generation characteristics in thermal inkjet recording devices) occur between recording elements or groups of recording elements. Due to variations in ejection characteristics (including ejection characteristics), unevenness occurs in recording density. Here, density unevenness due to variation between each element group is more problematic than density unevenness due to variation in each element within the element group.
本発明の目的は、このような欠点を除去し、各
記録要素群間の印字特性のばらつきを補正して、
濃度むらのない安定した記録画像を得るようにし
た記録装置の記録要素制御回路を提供することに
ある。 The purpose of the present invention is to eliminate such drawbacks, correct variations in printing characteristics between each recording element group, and
It is an object of the present invention to provide a recording element control circuit for a recording device that can obtain stable recorded images without density unevenness.
すなわち、本発明は、各記録要素群の印字特性
を予め測定し、この測定値に基いて、各要素群に
供給する電圧を制御するようにしたものである。 That is, in the present invention, the printing characteristics of each recording element group are measured in advance, and the voltages supplied to each element group are controlled based on the measured values.
以下、図面に基いて本発明を詳細に説明する。
以下で第１図、第２図と同様な箇所には同一の符
号を付して説明を進める。 Hereinafter, the present invention will be explained in detail based on the drawings.
In the following, parts similar to those in FIGS. 1 and 2 will be described with the same reference numerals.
第３図は、本発明制御回路を用いた記録装置の
１例を示す。ここで、HAは第４図に詳細を示す
記録要素アレー、VCは第５図に詳細を示す電圧
制御手段、SSは第１図、第２図において説明し
たと同様の信号供給源であり、取り出す信号のう
ち群選択信号SG１〜SG５６は第２図において説
明したと同様、トランジスタTRのオン・オフを
制御するための信号である。SL１′〜SL６′はSL
１〜SL６と同様の群選択信号であり、電圧制御
手段VCでの遅延時間を考慮して、ラツチ回路Ｌ
２に供給する群選択信号SL１〜SL６と異なつた
タイミングで電圧制御手段VCに供給される。 FIG. 3 shows an example of a recording device using the control circuit of the present invention. Here, HA is a recording element array whose details are shown in FIG. 4, VC is a voltage control means whose details are shown in FIG. 5, and SS is a signal supply source similar to that explained in FIGS. 1 and 2. Among the signals to be taken out, the group selection signals SG1 to SG56 are signals for controlling the on/off of the transistor TR, as explained in FIG. SL1' to SL6' are SL
This is a group selection signal similar to SL1 to SL6, and the latch circuit L is
The group selection signals SL1 to SL6 are supplied to the voltage control means VC at different timings from the group selection signals SL1 to SL6 supplied to the voltage control means VC.
第３図に基いて本発明の概略を説明する。今、
６ビツト信号SL１〜SL６，SL１′〜SL６′によ
り第１記録要素群Ｇ１，Ｇ２が順次に選択され、
信号SH１により要素群Ｇ１，Ｇ２の第１記録要
素Ｈ１を順次に発熱させるものとする。また、サ
ーマルヘツド記録装置を例にして、以下説明す
る。 The outline of the present invention will be explained based on FIG. now,
The first recording element groups G1 and G2 are sequentially selected by the 6-bit signals SL1 to SL6 and SL1' to SL6',
It is assumed that the first recording element H1 of the element groups G1 and G2 is sequentially heated by the signal SH1. Further, a description will be given below using a thermal head recording device as an example.
まず、電圧制御手段VCは、信号SL１′〜SL
６′に基いて、要素群Ｇ１の適正電圧HV１を記
録要素アレーHAに供給する。このとき要素群Ｇ
１に群選択信号SG１が、要素群Ｇ１の記録要素
Ｈ１に駆動信号SH１がそれぞれ供給されるので、
要素群Ｇ１の記録要素Ｈ１が発熱して、印字紙に
記録印字される。次いで、電圧制御手段VCは、
次に入来した信号SL１′〜SL６′に基いて、要素
群Ｇ２の適正電圧HV２を記録要素アレーHAに
供給する。このとき、要素群Ｇ２に群選択信号
SG２が、要素群Ｇ２の記録要素Ｈ１に駆動信号
SH１がそれぞれ供給されるので、要素群Ｇ２の
記録要素Ｈ１が発熱して、印字紙に記録印字され
る。 First, the voltage control means VC controls the signals SL1' to SL
6', the appropriate voltage HV1 of the element group G1 is supplied to the recording element array HA. At this time, element group G
Since the group selection signal SG1 is supplied to the recording element H1 of the element group G1 and the drive signal SH1 is supplied to the recording element H1 of the element group G1,
The recording element H1 of the element group G1 generates heat and records are printed on the printing paper. Then, the voltage control means VC is
Next, based on the incoming signals SL1' to SL6', the appropriate voltage HV2 of the element group G2 is supplied to the recording element array HA. At this time, a group selection signal is sent to the element group G2.
SG2 sends a drive signal to recording element H1 of element group G2.
Since SH1 is supplied respectively, the recording element H1 of the element group G2 generates heat and records are printed on the printing paper.
第４図は第３図示の記録要素アレーHAの１例
を示し、第２図に示す記録要素アレーHAとほぼ
同様であるが、本例においては、各要素群Ｇ１〜
Ｇ５６の各記録要素Ｈ１〜Ｈ３２に、各群の有す
る発熱特性による印字特性に合致した適正電圧
HViが電圧制御手段VCから供給される。 FIG. 4 shows an example of the recording element array HA shown in FIG. 3, which is almost the same as the recording element array HA shown in FIG.
Apply appropriate voltage to each recording element H1 to H32 of G56 that matches the printing characteristics due to the heat generation characteristics of each group.
HVi is supplied from voltage control means VC.
第５図は第３図示の電圧制御手段VCの１例を
示す。ここでは、記録要素群Ｇ１に適正電圧Ｖ１
を供給するものとして説明を進める。記憶手段と
しての読み取り専用メモリROMに、要素群Ｇ１
を選択すべき６ビツトの信号SL１′〜SL６′が供
給されると、メモリROMでは、次の電圧情報を
電圧供給手段を構成するＤ−ＡコンバータDAC
に供給する。すなわち、各要素群Ｇ１〜Ｇ５６の
印字特性のばらつきを考慮して、各要素群Ｇ１〜
Ｇ５６の適正電圧を予め測定しておき、その適正
電圧HViについての電圧情報が、メモリROMに
書き込んであるので、要素群Ｇ１についての電圧
情報がＤ−ＡコンバータDACに供給される。本
例では、メモリROMに書き込まれた電圧情報と
電源VEBからのバイアス電圧EBとを加算回路
ADで加算して適正電圧HV１を記録要素群Ｇ１
に供給する。 FIG. 5 shows an example of the voltage control means VC shown in FIG. Here, an appropriate voltage V1 is applied to the recording element group G1.
We will proceed with the explanation assuming that it supplies. The element group G1 is stored in the read-only memory ROM as a storage means.
When the 6-bit signals SL1' to SL6' for selecting the voltage are supplied, the memory ROM transmits the next voltage information to the D-A converter DAC constituting the voltage supply means.
supply to. That is, in consideration of variations in printing characteristics of each element group G1 to G56, each element group G1 to G56 is
Since the appropriate voltage of G56 has been measured in advance and voltage information regarding the appropriate voltage HVi has been written in the memory ROM, voltage information regarding the element group G1 is supplied to the D-A converter DAC. In this example, a circuit adds the voltage information written in the memory ROM and the bias voltage EB from the power supply VEB.
AD adds the appropriate voltage HV1 to recording element group G1.
supply to.
なお、バイアス電圧EBを加算せず、メモリ
ROMに直接、適正電圧HV１の値を書き込んで
もよいが、メモリROMの記憶容量を同一とすれ
ば、バイアス電圧EBを加算することにより、電
圧値をより高い精度で制御できる。例えば、各要
素群Ｇ１〜Ｇ５６の適正電圧が20V〜30Vの範囲
内にあり、メモリROMの容量を256ビツトとれ
ば、バイアス電圧EBとして20Vを印加しておく
ことにより、20V／256ビツト≒0.08Vごとに電圧
を制御できる。これに対し、バイアス電圧EBを
印加しない場合には、30V／256ビツト≒0.12Vご
とに電圧を制御することになる。また、逆に、電
圧の制御が粗くてもよい場合には、バイアス電圧
EBを印加するこことによりメモリROMの記憶容
量を低減することができる。 Note that without adding the bias voltage EB, the memory
The value of the appropriate voltage HV1 may be written directly into the ROM, but if the storage capacity of the memory ROM is the same, the voltage value can be controlled with higher precision by adding the bias voltage EB. For example, if the appropriate voltage for each element group G1 to G56 is within the range of 20V to 30V and the capacity of the memory ROM is 256 bits, by applying 20V as the bias voltage EB, 20V/256 bits ≒ 0.08 Voltage can be controlled for each V. On the other hand, when the bias voltage EB is not applied, the voltage is controlled every 30V/256 bits≈0.12V. Conversely, if coarse voltage control is acceptable, bias voltage
By applying EB, the storage capacity of the memory ROM can be reduced.
第６図は第３図示の電圧制御手属VCの他の例
を示すものである。本例では、各要素群Ｇ１〜Ｇ
５６に供給する適正電圧HViを、３つの電源VH，
VM，VLから得られる３通りの電圧HVH，HVM，
HVLとしたものであり、メモリROMには、各要
素群Ｇ１〜Ｇ５６に対して、３通りの適正電圧
HVH〜HVLのうちどれを選択するかという電圧
情報を書き込んでおく。例えば、要素群Ｇ１に対
しては電圧HVHを供給するものとすると、まず、
要素群Ｇ１を選択する６ビツトトの信号SL１′〜
SL６′がメモリROMに供給されると、メモリ
ROMは適正電圧HVHを選択し、その選択信号を
デコーダDEDに供給する。次いで、デコーダ
DEDから適正電源選択素子としてのトランジス
タTRHのベースにトランジスタオン信号が供給さ
れ、電源電圧HVHが選択される。しかして、適
正電圧HV１として電圧HVHが記録要素アレー
HAに供給される。なお、TRM，TRLはトランジ
スタ、DIH，DIM，DILはダイオードである。第６
図示の電圧制御手段VCは、各要素群間の発熱特
性に基づく印字特性のばらつきが少なく、微妙な
電圧制御を必要としない場合には十分に有効であ
る。 FIG. 6 shows another example of the voltage control member VC shown in FIG. 3. In this example, each element group G1 to G
The appropriate voltage HVi supplied to 56 is determined by three power supplies V H ,
Three voltages HV H , HV M , obtained from V M , V L ,
HV L , and the memory ROM has three appropriate voltages for each element group G1 to G56.
Write voltage information indicating which one to select from HV H to HV L. For example, assuming that voltage HV H is supplied to element group G1, first,
6-bit signal SL1' to select element group G1
When SL6' is supplied to the memory ROM, the memory
The ROM selects the appropriate voltage HV H and supplies the selection signal to the decoder DED. Then the decoder
A transistor-on signal is supplied from DED to the base of transistor TR H , which serves as an appropriate power source selection element, and power source voltage HV H is selected. Therefore, the voltage HV H is the appropriate voltage HV1 for the recording element array.
Supplied to HA. Note that TRM and TR L are transistors, and DI H , DIM and DIL are diodes. 6th
The illustrated voltage control means VC has little variation in printing characteristics based on heat generation characteristics between each element group, and is sufficiently effective when delicate voltage control is not required.
なお、以上の説明ではサーマツヘツド記録装置
を例にとつて説明したが、サーマルインクジエツ
ト記録装置においても同様に制御でき、この場合
には、各要素群の発熱特性を含んだ印字特性を測
定して、上述した供給電圧を制御すればよい。 Although the above explanation has been given using a thermal head recording device as an example, the same control can be applied to a thermal inkjet recording device, and in this case, the printing characteristics including the heat generation characteristics of each element group can be measured. , the above-mentioned supply voltage may be controlled.
以上説明したように、本発明によれば、ダイナ
ミツク駆動回路を用いて各記録要素群を制御する
場合に、各記録要素群の印字特性を考慮して、各
要素群に適正電圧を供給するようにしたので、各
要素群間の印字特性に起因した記録濃度むらの発
生を防止することができ、常に安定した記録画像
を得ることができる。 As explained above, according to the present invention, when controlling each recording element group using a dynamic drive circuit, an appropriate voltage is supplied to each element group in consideration of the printing characteristics of each recording element group. Therefore, it is possible to prevent the occurrence of recording density unevenness due to printing characteristics between each element group, and it is possible to always obtain a stable recorded image.
第１図は従来の記録要素制御回路の１例を示す
ブロツク図、第２図は既提案の記録要素制御回路
の１例を示すブロツク図、第３図は本発明記録要
素制御回路の１例を示すブロツク図、第４図はそ
の記録要素アレーの１例を示す回路図、第５図お
よび第６図は第３図示の回路の電圧制御手段の２
例を示すブロツク図である。
Ｇ１〜Ｇ５６……記録要素群、Ｈ１〜Ｈ３２…
…記録要素、DI，DIH，DIM，DIL……ダイオー
ド、SS……信号供給源、Ｌ１，Ｌ２……ラツチ
回路、DEC，DED……デコーダ、PC……パルス
幅制御回路、DS１，DS２……スイツチング素
子、TR，TRH，TRM，TRL……トランジスタ、
HA……記録要素アレー、VC……電圧制御手段、
ROM……メモリ、DAC……Ｄ−Ａコンバータ、
VEB……電源、AD……加算回路、PW，VH，
VM，VL……電源、SL１〜SL６，SL１′〜SL
６′，SG１〜SG５６……群選択信号、SH１〜
SH３２……要素駆動信号、CL……クロツク。
FIG. 1 is a block diagram showing an example of a conventional recording element control circuit, FIG. 2 is a block diagram showing an example of a previously proposed recording element control circuit, and FIG. 3 is an example of the recording element control circuit of the present invention. FIG. 4 is a circuit diagram showing one example of the recording element array, and FIGS. 5 and 6 are two voltage control means of the circuit shown in FIG. 3.
FIG. 2 is a block diagram showing an example. G1 to G56... recording element group, H1 to H32...
...recording element, DI, DI H , DI M , DI L ... diode, SS ... signal supply source, L1, L2 ... latch circuit, DEC, DED ... decoder, PC ... pulse width control circuit, DS1, DS2...Switching element, TR, TR H , TR M , TR L ...Transistor,
HA...recording element array, VC...voltage control means,
ROM...Memory, DAC...D-A converter,
VEB...Power supply, AD...Addition circuit, PW, V H ,
V M , V L ...Power supply, SL1~SL6, SL1'~SL
6', SG1~SG56...Group selection signal, SH1~
SH32...Element drive signal, CL...Clock.
Claims (1)
要素毎に配設され、当該記録要素のひとつを他の
前記記録要素から分離して駆動する分離駆動素子
とを有する記録要素群を複数個具備し、前記記録
要素のうち、所望の前記記録要素を前記記録要素
群毎に順次に発熱させて印字するようにした記録
装置の記録要素制御回路において、前記記録要素
群のそれぞれの印字特性に基いた適正電圧に関す
る電圧情報を前記記録要素群毎に記憶した記憶手
段と、該記憶手段から読み出された電圧情報に基
いて、前記記録要素群に前記適正電圧を供給する
電圧供給手段とを具備したことを特徴とする記録
装置の記録要素制御回路。 ２ 特許請求の範囲第１項記載の制御回路におい
て、前記電圧情報として、前記記録要素毎の前記
適正電圧を前記記憶手段に記憶し、当該記憶手段
から読み出された前記適正電圧を前記記録要素群
に供給するようにしたことを特徴とする記録装置
の記録要素制御回路。 ３ 特許請求の範囲第１項記載の制御回路におい
て、前記記憶手段から読み出された前記電圧情報
としての所定電圧に所定のバイアス電圧を加算し
て前記適正電圧を得る加算回路を有し、該加算回
路の出力を前記記録要素群に供給するようにした
ことを特徴とする記録装置の記録要素制御回路。 ４ 特許請求の範囲第１項記載の制御回路におい
て、前記電圧供給手段は、少なくとも１以上の適
正電圧電源と、前記記憶手段から読み出された前
記電圧情報に基いて前記適正電圧電源のいずれか
を選択する電源選択素子とを有し、前記電源選択
素子により前記適正電圧電源のひとつを選択して
前記記録要素群に前記適正電圧を順次供給するよ
うにしたことを特徴とする記録装置の記録要素制
御回路。 ５ 特許請求の範囲第１項〜第４項のいずれかに
記載の制御回路において、前記分離駆動素子をト
ランジスタとしたことを特徴とする記録装置の記
録要素制御回路。[Claims] 1. A recording element having at least a recording element having a heating element, and a separation drive element disposed for each recording element and driving one of the recording elements separately from the other recording elements. In a recording element control circuit of a recording apparatus, which includes a plurality of groups of recording elements, and prints by sequentially heating a desired recording element among the recording element groups for each of the recording element groups, each of the recording element groups a storage means that stores voltage information regarding an appropriate voltage based on printing characteristics for each recording element group; and a voltage for supplying the appropriate voltage to the recording element group based on the voltage information read from the storage means. 1. A recording element control circuit for a recording device, comprising: supply means. 2. In the control circuit according to claim 1, the appropriate voltage for each recording element is stored in the storage means as the voltage information, and the appropriate voltage read from the storage means is used as the voltage information for the recording element. 1. A recording element control circuit for a recording device, characterized in that the circuit supplies a recording element to a group of recording elements. 3. The control circuit according to claim 1, further comprising an adding circuit for obtaining the appropriate voltage by adding a predetermined bias voltage to the predetermined voltage as the voltage information read from the storage means, A recording element control circuit for a recording apparatus, characterized in that the output of the adder circuit is supplied to the recording element group. 4. In the control circuit according to claim 1, the voltage supply means is configured to supply at least one appropriate voltage power source and one of the appropriate voltage power sources based on the voltage information read from the storage means. a power source selection element for selecting one of the appropriate voltage power sources, the power source selection element selects one of the appropriate voltage power sources to sequentially supply the appropriate voltage to the recording element group. Element control circuit. 5. A printing element control circuit for a printing apparatus, wherein the control circuit according to any one of claims 1 to 4, wherein the separation drive element is a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11113080A JPS5736682A (en) | 1980-08-14 | 1980-08-14 | Recording element controlling circuit for recorder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11113080A JPS5736682A (en) | 1980-08-14 | 1980-08-14 | Recording element controlling circuit for recorder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5736682A JPS5736682A (en) | 1982-02-27 |
| JPS647591B2 true JPS647591B2 (en) | 1989-02-09 |
Family
ID=14553197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11113080A Granted JPS5736682A (en) | 1980-08-14 | 1980-08-14 | Recording element controlling circuit for recorder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5736682A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3225398A1 (en) | 2016-03-31 | 2017-10-04 | Brother Kogyo Kabushiki Kaisha | Control circuit, ink-jet head system, and control method |
| JP2018047605A (en) * | 2016-09-21 | 2018-03-29 | ブラザー工業株式会社 | Power source selection circuit, circuit, head module, and printer |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58194461A (en) * | 1982-05-07 | 1983-11-12 | Ricoh Co Ltd | Processing system of picture information |
| JPS6078769A (en) * | 1983-10-05 | 1985-05-04 | Fujitsu Ltd | Thermal recording system |
| JPH0679853B2 (en) * | 1983-12-09 | 1994-10-12 | キヤノン株式会社 | Liquid ejector |
| JPS60109941U (en) * | 1983-12-28 | 1985-07-25 | ロ−ム株式会社 | Thermal head power supply voltage setting circuit |
| JPH0698757B2 (en) * | 1986-06-13 | 1994-12-07 | 富士ゼロックス株式会社 | Inkjet recording method |
| JP7367405B2 (en) * | 2019-09-04 | 2023-10-24 | ブラザー工業株式会社 | Printing device and printing method |
-
1980
- 1980-08-14 JP JP11113080A patent/JPS5736682A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3225398A1 (en) | 2016-03-31 | 2017-10-04 | Brother Kogyo Kabushiki Kaisha | Control circuit, ink-jet head system, and control method |
| JP2017177755A (en) * | 2016-03-31 | 2017-10-05 | ブラザー工業株式会社 | Control circuit, inkjet head system, and control method |
| US10391765B2 (en) | 2016-03-31 | 2019-08-27 | Brother Kogyo Kabushiki Kaisha | Control circuit, ink-jet head system, and control method |
| JP2018047605A (en) * | 2016-09-21 | 2018-03-29 | ブラザー工業株式会社 | Power source selection circuit, circuit, head module, and printer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5736682A (en) | 1982-02-27 |
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