JPS6474673A - Control system for address conversion of vector processor - Google Patents

Control system for address conversion of vector processor

Info

Publication number
JPS6474673A
JPS6474673A JP62231386A JP23138687A JPS6474673A JP S6474673 A JPS6474673 A JP S6474673A JP 62231386 A JP62231386 A JP 62231386A JP 23138687 A JP23138687 A JP 23138687A JP S6474673 A JPS6474673 A JP S6474673A
Authority
JP
Japan
Prior art keywords
address conversion
dynamic address
control system
invalidity
validity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62231386A
Other languages
Japanese (ja)
Inventor
Masatake Iwato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62231386A priority Critical patent/JPS6474673A/en
Publication of JPS6474673A publication Critical patent/JPS6474673A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To optionally use properly both static and dynamic address conversion systems as necessary for improvement of the operating efficiency of the titled control system, by selecting freely either one of said two address conversion systems in accordance with presence or absence and validity or invalidity of the dynamic address conversion. CONSTITUTION:A vector control register 5 displays the hardware characteristics (presence or absence of the dynamic address conversion) and the software characteristics (validity or invalidity of the dynamic address conversion). Based on this display, a vector instruction control circuit 6 performs the static address conversion with absence and invalidity of the dynamic address conversion and then the dynamic address conversion with presence and validity of the dynamic address conversion respectively. In case of the static address conversion, the circuit 6 carries out the advance control and the parallel processes to a vector processing part 7. While the circuit 6 produces an arithmetic instruction without carrying out the advance control nor parallel processes in case of the dynamic address conversion. Thus the operating efficiency is improved with a control system for address conversion.
JP62231386A 1987-09-16 1987-09-16 Control system for address conversion of vector processor Pending JPS6474673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62231386A JPS6474673A (en) 1987-09-16 1987-09-16 Control system for address conversion of vector processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62231386A JPS6474673A (en) 1987-09-16 1987-09-16 Control system for address conversion of vector processor

Publications (1)

Publication Number Publication Date
JPS6474673A true JPS6474673A (en) 1989-03-20

Family

ID=16922798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62231386A Pending JPS6474673A (en) 1987-09-16 1987-09-16 Control system for address conversion of vector processor

Country Status (1)

Country Link
JP (1) JPS6474673A (en)

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