JPS6474656A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6474656A
JPS6474656A JP23293287A JP23293287A JPS6474656A JP S6474656 A JPS6474656 A JP S6474656A JP 23293287 A JP23293287 A JP 23293287A JP 23293287 A JP23293287 A JP 23293287A JP S6474656 A JPS6474656 A JP S6474656A
Authority
JP
Japan
Prior art keywords
circuits
circuit
connection
function
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23293287A
Other languages
Japanese (ja)
Inventor
Wataru Shimoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23293287A priority Critical patent/JPS6474656A/en
Publication of JPS6474656A publication Critical patent/JPS6474656A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To connect circuits with four connection circuits to reduce the number of connection circuits by using the connection circuits where register circuits are added to transceiver circuits in a connection means of four function circuits included in the titled data processor. CONSTITUTION:Transfer between adjacent function circuits in case of transfer in one direction is completed with one processing by a data bus set through the transceiver circuit. In case of transfer between function circuits on a diagonal line like function circuits 1 and 3, output data of the circuit 1 is stored in a register circuit 82 of the circuit 8 by first processing. Meanwhile, output data of the circuit 3 is stored in a register circuit 62 of a connection circuit 6. Out put data of circuits 82 and 62 are sent to circuits 3 and 1 through transceiver circuits 71 and 51 of connection circuits 7 and 5 respectively by second processing. Thus, function circuits are connected by four connection circuits to reduce the number of circuits.
JP23293287A 1987-09-16 1987-09-16 Data processor Pending JPS6474656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23293287A JPS6474656A (en) 1987-09-16 1987-09-16 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23293287A JPS6474656A (en) 1987-09-16 1987-09-16 Data processor

Publications (1)

Publication Number Publication Date
JPS6474656A true JPS6474656A (en) 1989-03-20

Family

ID=16947107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23293287A Pending JPS6474656A (en) 1987-09-16 1987-09-16 Data processor

Country Status (1)

Country Link
JP (1) JPS6474656A (en)

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