JPS6474623A - Instruction control system - Google Patents

Instruction control system

Info

Publication number
JPS6474623A
JPS6474623A JP23182887A JP23182887A JPS6474623A JP S6474623 A JPS6474623 A JP S6474623A JP 23182887 A JP23182887 A JP 23182887A JP 23182887 A JP23182887 A JP 23182887A JP S6474623 A JPS6474623 A JP S6474623A
Authority
JP
Japan
Prior art keywords
instruction
return
return instruction
subroutine
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23182887A
Other languages
Japanese (ja)
Inventor
Masahito Hihara
Chikako Kariyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23182887A priority Critical patent/JPS6474623A/en
Publication of JPS6474623A publication Critical patent/JPS6474623A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To prevent the degradation of throughput even at the time of providing a subroutine by detecting a return instruction and returning the control to a main routine and in case of running in the sublevel, skipping the return instruction during running in the main level. CONSTITUTION:An instruction deciding circuit 8 decides and detects whether the instruction which is read out from a memory 6 and is held in an OPR 7 is a return instruction or not. A return instruction is inserted to the end of a subroutine in the main routine, and the return destination address is stored in an ADR 5 to return to and continue the original processing when the system is run in the sublevel if the return instruction is detected during execution of the processing by the circuit 8. When the system is run in the main level then, this return instruction is skipped to continue the processing. Thus, the subroutine is easily provided in the main routine to prevent the degradation of the throughput.
JP23182887A 1987-09-16 1987-09-16 Instruction control system Pending JPS6474623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23182887A JPS6474623A (en) 1987-09-16 1987-09-16 Instruction control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23182887A JPS6474623A (en) 1987-09-16 1987-09-16 Instruction control system

Publications (1)

Publication Number Publication Date
JPS6474623A true JPS6474623A (en) 1989-03-20

Family

ID=16929656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23182887A Pending JPS6474623A (en) 1987-09-16 1987-09-16 Instruction control system

Country Status (1)

Country Link
JP (1) JPS6474623A (en)

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