JPS6473828A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6473828A
JPS6473828A JP23061187A JP23061187A JPS6473828A JP S6473828 A JPS6473828 A JP S6473828A JP 23061187 A JP23061187 A JP 23061187A JP 23061187 A JP23061187 A JP 23061187A JP S6473828 A JPS6473828 A JP S6473828A
Authority
JP
Japan
Prior art keywords
circuit
output
value
holding part
held
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23061187A
Other languages
Japanese (ja)
Inventor
Hiroyuki Kono
Keisuke Okada
Sumitaka Takeuchi
Masatoshi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23061187A priority Critical patent/JPS6473828A/en
Publication of JPS6473828A publication Critical patent/JPS6473828A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To obtain a fast and highly integrated semiconductor integrated circuit, by outputting the maximum value or the minimum value by inputting the output of a comparator directly to an OR circuit or an AND circuit. CONSTITUTION:The titled circuit is constituted of a first holding part 7 which holds the output of the comparator, a second holding part 8 which holds a peak value (maximum value), the OR circuit 9 which takes out a larger value out of the values held at the holding parts 7 and 8, and a control circuit 10 which controls a timing to transmit the maximum value held at the holding part 8 to an encoder circuit. The output of the OR circuit is held at the second holding part 8, and it is inputted to the encoder circuit 5 by operating the control circuit 10. Thus, by constituting an A/D converter of parallel comparison system, it is possible to output the peak value of analog input and an A/D conversion value to an output terminal 6.
JP23061187A 1987-09-14 1987-09-14 Semiconductor integrated circuit Pending JPS6473828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23061187A JPS6473828A (en) 1987-09-14 1987-09-14 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23061187A JPS6473828A (en) 1987-09-14 1987-09-14 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6473828A true JPS6473828A (en) 1989-03-20

Family

ID=16910475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23061187A Pending JPS6473828A (en) 1987-09-14 1987-09-14 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6473828A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05503196A (en) * 1990-02-16 1993-05-27 シーメンス　ニクスドルフ　インフオルマチオーンス　ジステーメ　アクチエンゲゼルシヤフト How to convert analog voltage to digital value

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05503196A (en) * 1990-02-16 1993-05-27 シーメンス　ニクスドルフ　インフオルマチオーンス　ジステーメ　アクチエンゲゼルシヤフト How to convert analog voltage to digital value

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