JPS6472639A - Device monitoring method - Google Patents

Device monitoring method

Info

Publication number
JPS6472639A
JPS6472639A JP22834487A JP22834487A JPS6472639A JP S6472639 A JPS6472639 A JP S6472639A JP 22834487 A JP22834487 A JP 22834487A JP 22834487 A JP22834487 A JP 22834487A JP S6472639 A JPS6472639 A JP S6472639A
Authority
JP
Japan
Prior art keywords
monitored
parity
data series
generating circuit
random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22834487A
Other languages
Japanese (ja)
Inventor
Eiichi Kabaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22834487A priority Critical patent/JPS6472639A/en
Publication of JPS6472639A publication Critical patent/JPS6472639A/en
Pending legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To sufficiently attain the monitor of device independently of the input data series by applying parity check of data outputted by a device to be monitored so as to device whether or not the device to be monitored is operated correctly. CONSTITUTION:A pattern generating circuit 4 generates a random data series whose pattern is random, an adder 6 codes the input data series DIN1-DINn as a random pattern and the sum of modulo 2 with the random data series generated by the pattern generating circuit 4 with the input data series is calculated and the result is outputted to the monitored device 1 and a parity generating circuit 2. The parity generating circuit 2 generates a parity bit based on the data from an adder 6, and the adder 6 adds it to a data inputted to the monitored device 1. Then a parity collation circuit 3 checks the parity of the data including the parity bit outputted from the monitored device 1 to device whether or not the monitored device is operated correctly. Thus, the device is monitored sufficiently independently of the input data series.
JP22834487A 1987-09-14 1987-09-14 Device monitoring method Pending JPS6472639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22834487A JPS6472639A (en) 1987-09-14 1987-09-14 Device monitoring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22834487A JPS6472639A (en) 1987-09-14 1987-09-14 Device monitoring method

Publications (1)

Publication Number Publication Date
JPS6472639A true JPS6472639A (en) 1989-03-17

Family

ID=16874990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22834487A Pending JPS6472639A (en) 1987-09-14 1987-09-14 Device monitoring method

Country Status (1)

Country Link
JP (1) JPS6472639A (en)

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