JPS6470849A - Home bus controller - Google Patents

Home bus controller

Info

Publication number
JPS6470849A
JPS6470849A JP62226678A JP22667887A JPS6470849A JP S6470849 A JPS6470849 A JP S6470849A JP 62226678 A JP62226678 A JP 62226678A JP 22667887 A JP22667887 A JP 22667887A JP S6470849 A JPS6470849 A JP S6470849A
Authority
JP
Japan
Prior art keywords
abnormality
bus
bit
controller
bus controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62226678A
Other languages
Japanese (ja)
Inventor
Masato Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62226678A priority Critical patent/JPS6470849A/en
Publication of JPS6470849A publication Critical patent/JPS6470849A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To simply and easily detected the abnormality of a bus by utilizing a start bit of a command and allowing a home bus controller to detect the abnormality of the bit to decide the abnormality of the bus. CONSTITUTION:When an interface unit 8 in a connecting apparatus 11 e.g. connected to a bus 6 is failed or the apparatus 11 is an off-specification connecting apparatus mismatching its connection, the impedance of the bus 6 is dropped, the normal transmission of a control signal transmitted from a home bus controller 9 by the bus 6 through an interface unit 7 is disabled, so that the level of the start bit 12 added to the shown control signal (command) to be sent is dropped. Thus, the abnormality of the start bit 12 is detected by allowing the controller 9 to always receive and monitor the bit 12 by utilizing the said status, and at the time of detecting the abnormality of the bit 12, displays the abnormality on a display device 10 as abnormality to inform it to the external.
JP62226678A 1987-09-11 1987-09-11 Home bus controller Pending JPS6470849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62226678A JPS6470849A (en) 1987-09-11 1987-09-11 Home bus controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62226678A JPS6470849A (en) 1987-09-11 1987-09-11 Home bus controller

Publications (1)

Publication Number Publication Date
JPS6470849A true JPS6470849A (en) 1989-03-16

Family

ID=16848936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62226678A Pending JPS6470849A (en) 1987-09-11 1987-09-11 Home bus controller

Country Status (1)

Country Link
JP (1) JPS6470849A (en)

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