JPS6468954A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6468954A
JPS6468954A JP22740587A JP22740587A JPS6468954A JP S6468954 A JPS6468954 A JP S6468954A JP 22740587 A JP22740587 A JP 22740587A JP 22740587 A JP22740587 A JP 22740587A JP S6468954 A JPS6468954 A JP S6468954A
Authority
JP
Japan
Prior art keywords
resin film
semiconductor device
resin
sealing
leakage current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22740587A
Other languages
Japanese (ja)
Inventor
Tsunemitsu Koda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22740587A priority Critical patent/JPS6468954A/en
Publication of JPS6468954A publication Critical patent/JPS6468954A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Injection Moulding Of Plastics Or The Like (AREA)
  • Adhesive Tapes (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To produce a semiconductor device in which no leakage current is present between leads thereof, by employing a series of processes in which a semiconductor device is assembled using a resin film and the resin film is then removed, a resin sealing being thereafter performed. CONSTITUTION:A semiconductor device loading part 1 and inner leads 2 of a lead frame are relatively fixed on a resin film 3 of which bonding strength is weakened by irradiation of ultraviolet rays. Under this fixed condition, a die bonding of a semiconductor device 4 is performed, and a wire bonding is then performed using metal fine wires 5. Under this condition, the resin film 3 is irradiated with ultraviolet rays to weaken the bonding strength thereof. Subsequently, the resin film 3 is peeled off, sealing is thereafter performed with a resin 6. As a result, during a resin sealing process, the resin film, which causes leakage current to be increased, needn't be employed.
JP22740587A 1987-09-09 1987-09-09 Manufacture of semiconductor device Pending JPS6468954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22740587A JPS6468954A (en) 1987-09-09 1987-09-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22740587A JPS6468954A (en) 1987-09-09 1987-09-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6468954A true JPS6468954A (en) 1989-03-15

Family

ID=16860316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22740587A Pending JPS6468954A (en) 1987-09-09 1987-09-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6468954A (en)

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