JPS6466734A - Program translating method - Google Patents

Program translating method

Info

Publication number
JPS6466734A
JPS6466734A JP22300087A JP22300087A JPS6466734A JP S6466734 A JPS6466734 A JP S6466734A JP 22300087 A JP22300087 A JP 22300087A JP 22300087 A JP22300087 A JP 22300087A JP S6466734 A JPS6466734 A JP S6466734A
Authority
JP
Japan
Prior art keywords
dag
route length
instruction
constitution
tree
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22300087A
Other languages
Japanese (ja)
Inventor
Isaaki Uchiumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP22300087A priority Critical patent/JPS6466734A/en
Publication of JPS6466734A publication Critical patent/JPS6466734A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/441—Register allocation; Assignment of physical memory space to logical memory space

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE:To decrease the total number of executing steps by detecting a path of the maximum route length in a DAG produced from the codes of the pipleline architecture and allocating a register to an instruction node set on said path. CONSTITUTION:A 4-set code generating part 1 analyzes the syntax structure of a source program to turn this program into the 4-set codes. A DAG producing part 2 produces a DAG from said 4-set codes and calculates the route length from the leaf against each node in the DAG. At a tree constitution converting part 3 of an addition/multiplication part, the constitution of a partial tree is changed so that the route length between the leaf and the tree root is minimized against the partial tree of the continuous addition or multiplication. A register allocation part 4 allocates the registers successively to the instruction nodes set on a path having the maximum route length from the root of the DAG. An instruction rearrangement part 5 takes out the instruction nodes toward the leaf from the root and rearranges the instructions.
JP22300087A 1987-09-08 1987-09-08 Program translating method Pending JPS6466734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22300087A JPS6466734A (en) 1987-09-08 1987-09-08 Program translating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22300087A JPS6466734A (en) 1987-09-08 1987-09-08 Program translating method

Publications (1)

Publication Number Publication Date
JPS6466734A true JPS6466734A (en) 1989-03-13

Family

ID=16791249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22300087A Pending JPS6466734A (en) 1987-09-08 1987-09-08 Program translating method

Country Status (1)

Country Link
JP (1) JPS6466734A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015143939A (en) * 2014-01-31 2015-08-06 富士通株式会社 Compilation program, compilation method, and compilation device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015143939A (en) * 2014-01-31 2015-08-06 富士通株式会社 Compilation program, compilation method, and compilation device
US9823911B2 (en) 2014-01-31 2017-11-21 Fujitsu Limited Method and apparatus for compiling code based on a dependency tree

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