JPS646597Y2 - - Google Patents
Info
- Publication number
- JPS646597Y2 JPS646597Y2 JP10125284U JP10125284U JPS646597Y2 JP S646597 Y2 JPS646597 Y2 JP S646597Y2 JP 10125284 U JP10125284 U JP 10125284U JP 10125284 U JP10125284 U JP 10125284U JP S646597 Y2 JPS646597 Y2 JP S646597Y2
- Authority
- JP
- Japan
- Prior art keywords
- output
- amplifier
- comparator
- detector
- power amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003321 amplification Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Description
【考案の詳細な説明】
この考案は無線機に用いられる自動電力制御回
路に関するものである。[Detailed Description of the Invention] This invention relates to an automatic power control circuit used in radio equipment.
(従来技術とその問題点)
第2図に従来の自動電力制御回路(以下APC
回路)を示す。電力増幅器(以下PA)1の出力
は帯域通過フイルタ(BPF)2を通してアンテ
ナ3から放射される。このPA1の出力を結合し、
外部制御信号端子5から制御される可変抵抗器4
により減衰させ、検波器6により直流に変換す
る。この直流は抵抗8,9を通り、比較・増幅器
11により増幅され、PA1の電源端子に入り、
送信出力を制御する。この回路によつて制御され
るPA1はその電圧対出力特性が直線的でないた
め、広い範囲にわたり電力を制御しようとする
と、ループ利得が変化し、利得の高いとき発振し
やすく、また利得の低いとき電源電圧変動が大き
くなる。これを改良するため、従来は比較・増幅
器の入力抵抗8に並列にFETのドレイン・ソー
スを接続し、ゲートを外部制御端子5の1つに接
続し、これによりFETをON.OFFさせ、比較増
幅器11の増幅度を変え、ループ利得を変化させ
ていたが、PA1の品種が異なると、電圧対出力
特性が異なるため、FETを動作させる制御信号
を外部制御端子5の別の信号に変えなければなら
ないか、または和をとる必要があり、回路変更が
必要であつた。(Prior art and its problems) Figure 2 shows a conventional automatic power control circuit (APC).
circuit). The output of a power amplifier (hereinafter referred to as PA) 1 is radiated from an antenna 3 through a band pass filter (BPF) 2. Combine the output of this PA1,
Variable resistor 4 controlled from external control signal terminal 5
It is attenuated by the detector 6 and converted to direct current by the detector 6. This DC passes through resistors 8 and 9, is amplified by comparator/amplifier 11, enters the power supply terminal of PA1,
Control transmit power. PA1 controlled by this circuit has a non-linear voltage vs. output characteristic, so when trying to control power over a wide range, the loop gain changes, and when the gain is high it tends to oscillate, and when the gain is low it tends to oscillate. Power supply voltage fluctuations increase. In order to improve this, conventionally the drain and source of the FET were connected in parallel to the input resistor 8 of the comparator/amplifier, and the gate was connected to one of the external control terminals 5, thereby turning the FET ON and OFF, and making a comparison. The loop gain was changed by changing the amplification degree of the amplifier 11, but since different types of PA1 have different voltage vs. output characteristics, the control signal for operating the FET must be changed to a different signal at the external control terminal 5. The circuit must be changed or the sum must be calculated.
(目的)
本考案はAPCの電力増幅器の品種が異なる等
により、電圧対出力特性が変わつた場合におい
て、その対策としてとられる比較・増幅器の増幅
度の変更を簡易な手段で行うものである。(Purpose) This invention is a simple means to change the amplification degree of the comparison/amplifier as a countermeasure when the voltage vs. output characteristics change due to different types of APC power amplifiers.
(考案の構成)
本考案は電力増幅器、可変抵抗器、検波器およ
び比較・増幅器で閉ループを構成する自動電力制
御回路において、比較・増幅器の入力抵抗に並列
にFETのドレイン、ソースを接続し、かつ上記
電力増幅器の出力端とFETのゲート端子間に第
2の検波器を接続する構成にし、電力増幅器の出
力でFETを制御し比較・増幅器の増幅度を変え
ようとするものである。(Structure of the invention) This invention is an automatic power control circuit that configures a closed loop with a power amplifier, a variable resistor, a detector, and a comparator/amplifier. In addition, a second detector is connected between the output terminal of the power amplifier and the gate terminal of the FET, and the FET is controlled by the output of the power amplifier to change the amplification degree of the comparison/amplifier.
(実施例)
第1図は本考案の実施例である。PA1の出力
に可変抵抗器4を接続し、その後検波器6、入力
抵抗8,9を介して比較・増幅器11に接続し、
その出力はPA1の電源に接続する。またPA1の
出力とアース間に抵抗12および13を接続し、
その抵抗12と13の接続点にダイオード14の
アノードを接続し、カソード・アース間にコンデ
ンサ15を接続する。このカソードはさらに入力
抵抗8に並列にドレイン・ソースを接続した
FET7のゲートに接続する。(Example) FIG. 1 shows an example of the present invention. A variable resistor 4 is connected to the output of PA1, and then connected to a comparator/amplifier 11 via a detector 6 and input resistors 8 and 9.
Its output is connected to the power supply of PA1. Also, connect resistors 12 and 13 between the output of PA1 and the ground,
The anode of a diode 14 is connected to the connection point between the resistors 12 and 13, and a capacitor 15 is connected between the cathode and ground. The drain and source of this cathode were further connected in parallel to the input resistor 8.
Connect to the gate of FET7.
以下この動作について説明する。APC回路の
基本動作は第1図に示した従来の回路と同様であ
る。PA1の出力の一部は抵抗12,13によつ
て取り出され、この出力はダイオード14および
コンデンサ15により検波され、直流電圧にな
り、この電圧は抵抗12および13により決定さ
れる。PA1の出力が大きいときこの検波電圧も
高くなり、FET7のドレイン・ソース間が導通
し、比較・増幅器11の利得Aは抵抗8,9,1
0の値をそれぞれR1,R2,R3とするとA=
R3/R2となる。一方出力が小さいとゲート電
圧が低くなりFETがOFF状態になるのでA=R
3/(R1+R2)となる。このようにしてPA
1の出力の大小と抵抗の定数によりAPC回路の
ループ利得を変えることができるので、従来の制
御信号を利用した回路のようにPA1の品種が異
なつても回路の変更を行なう必要がない。 This operation will be explained below. The basic operation of the APC circuit is similar to the conventional circuit shown in FIG. A part of the output of PA1 is taken out by resistors 12 and 13, and this output is detected by diode 14 and capacitor 15 to become a DC voltage, which voltage is determined by resistors 12 and 13. When the output of PA1 is large, this detection voltage also becomes high, conduction occurs between the drain and source of FET7, and the gain A of comparator/amplifier 11 is increased by resistors 8, 9, and 1.
If the values of 0 are R1, R2, and R3, then A=
It becomes R3/R2. On the other hand, if the output is small, the gate voltage will be low and the FET will be in the OFF state, so A = R
3/(R1+R2). In this way P.A.
Since the loop gain of the APC circuit can be changed depending on the magnitude of the output of PA1 and the constant of the resistor, there is no need to change the circuit even if the type of PA1 differs, unlike in conventional circuits that use control signals.
(効果)
本考案によるAPC回路は、種々のPAに適用が
可能であり、従来に比べ、汎用性が大きくなる。(Effects) The APC circuit according to the present invention can be applied to various PAs, and has greater versatility than conventional circuits.
第2図は従来のAPC回路、第1図:本考案の
実施例。
1……PA、2……BPF、3……アンテナ、4
……可変抵抗器、5……外部制御信号、6……検
波器、7……FET、8,9,10,12,13
……抵抗、11……比較・増幅器、14……ダイ
オード、15……コンデンサ。
Figure 2 shows a conventional APC circuit, Figure 1 shows an embodiment of the present invention. 1...PA, 2...BPF, 3...antenna, 4
... Variable resistor, 5 ... External control signal, 6 ... Detector, 7 ... FET, 8, 9, 10, 12, 13
...Resistor, 11... Comparison/amplifier, 14... Diode, 15... Capacitor.
Claims (1)
して可変抵抗器、第1の検波器および比較・増幅
器を通して電力増幅器の出力を制御する自動電力
制御回路において、比較・増幅器の入力抵抗に並
列にFETのドレイン、ソースを接続し、ゲート
端子を電力増幅の出力に接続した第2の検波器に
接続することを特徴とした自動電力制御回路。 In a mobile radio, in an automatic power control circuit that combines the output of a power amplifier and controls the output of the power amplifier through a variable resistor, a first detector, and a comparator/amplifier, a FET is connected in parallel to the input resistance of the comparator/amplifier. An automatic power control circuit characterized in that the drain and source of the power amplifier are connected to a second detector whose gate terminal is connected to the output of the power amplifier.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10125284U JPS6118646U (en) | 1984-07-06 | 1984-07-06 | automatic power control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10125284U JPS6118646U (en) | 1984-07-06 | 1984-07-06 | automatic power control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6118646U JPS6118646U (en) | 1986-02-03 |
JPS646597Y2 true JPS646597Y2 (en) | 1989-02-21 |
Family
ID=30660691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10125284U Granted JPS6118646U (en) | 1984-07-06 | 1984-07-06 | automatic power control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6118646U (en) |
-
1984
- 1984-07-06 JP JP10125284U patent/JPS6118646U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6118646U (en) | 1986-02-03 |
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