JPS6465950A - Self-routing channel - Google Patents

Self-routing channel

Info

Publication number
JPS6465950A
JPS6465950A JP22247187A JP22247187A JPS6465950A JP S6465950 A JPS6465950 A JP S6465950A JP 22247187 A JP22247187 A JP 22247187A JP 22247187 A JP22247187 A JP 22247187A JP S6465950 A JPS6465950 A JP S6465950A
Authority
JP
Japan
Prior art keywords
packets
inputted
bits
channel
cycling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22247187A
Other languages
Japanese (ja)
Inventor
Koichi Hagishima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP22247187A priority Critical patent/JPS6465950A/en
Publication of JPS6465950A publication Critical patent/JPS6465950A/en
Pending legal-status Critical Current

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To eliminate the delay fluctuation of packets by fetching routing control information bits into a holding circuit, causing them to cycle and shift in a cycle type register and switching the path of the packets. CONSTITUTION:A serial-parallel conversion circuit 16 outputs the packets inputted from input lines 14 to eight (=n) output lines one by one by cycling, and they are inputted to eight planes 101-1-1-101-1-8 in a channel stage. In channel stages 12 and 13, bits 2a and 3a are fetched into the holding circuit 112, a unit switch 111 is controlled while the packets are shifted by cycling and the routing of the packets are executed in the same way as the channel stage 11. Thus, the signals >= two bits are not simultaneously inputted to eight input lines of respective planes 101 in the channels 11-13. Consequently, the inputted signals can reach the final channel stage 13 without collision in an internal link.
JP22247187A 1987-09-04 1987-09-04 Self-routing channel Pending JPS6465950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22247187A JPS6465950A (en) 1987-09-04 1987-09-04 Self-routing channel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22247187A JPS6465950A (en) 1987-09-04 1987-09-04 Self-routing channel

Publications (1)

Publication Number Publication Date
JPS6465950A true JPS6465950A (en) 1989-03-13

Family

ID=16782934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22247187A Pending JPS6465950A (en) 1987-09-04 1987-09-04 Self-routing channel

Country Status (1)

Country Link
JP (1) JPS6465950A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01105641A (en) * 1987-10-19 1989-04-24 Oki Electric Ind Co Ltd Packet switching system
JPH03241945A (en) * 1990-02-19 1991-10-29 Nec Corp Cross connector

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01105641A (en) * 1987-10-19 1989-04-24 Oki Electric Ind Co Ltd Packet switching system
JPH03241945A (en) * 1990-02-19 1991-10-29 Nec Corp Cross connector

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