JPS646563B2 - - Google Patents
Info
- Publication number
- JPS646563B2 JPS646563B2 JP8969683A JP8969683A JPS646563B2 JP S646563 B2 JPS646563 B2 JP S646563B2 JP 8969683 A JP8969683 A JP 8969683A JP 8969683 A JP8969683 A JP 8969683A JP S646563 B2 JPS646563 B2 JP S646563B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- diode
- temperature
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000013016 damping Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/24—Frequency- independent attenuators
- H03H7/25—Frequency- independent attenuators comprising an element controlled by an electric or magnetic variable
- H03H7/253—Frequency- independent attenuators comprising an element controlled by an electric or magnetic variable the element being a diode
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/54—Modifications of networks to reduce influence of variations of temperature
Landscapes
- Attenuators (AREA)
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、PINダイオードを用いた定インピー
ダンス形の可変抵抗減衰回路に関する。特に、
PINダイオードに与えるバイアス電圧を温度補償
型にした可変抵抗減衰回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a constant impedance type variable resistance attenuation circuit using a PIN diode. especially,
This paper relates to an improvement of a variable resistance attenuation circuit in which the bias voltage applied to the PIN diode is temperature-compensated.
第１図は改良前の回路構成図である。定インピ
ーダンス抵抗減衰器１の入力端子１ａには高周波
信号が入力し、減衰を受けて出力端子１ｂに送出
される。この定インピーダンス抵抗減衰器１は橋
絡Ｔ形の可変抵抗減衰器である。この定インピー
ダンス抵抗減衰器１には、その直列アームおよび
並列アームにそれぞれPINダイオード１ｃおよび
１ｄを備え、その直流バイアス電圧を与える回路
は、２個のコイル１ｆおよび１ｇにより直列に接
続されている。この直流バイアス電圧を与える電
源端子１ｈには直流バイアス電圧発生回路から直
流バイアス電圧が与えられ、上記２個のコイルの
接続点である制御端子１ｋには制御電圧が与えら
れる。
FIG. 1 is a circuit configuration diagram before improvement. A high frequency signal is input to the input terminal 1a of the constant impedance resistance attenuator 1, and is attenuated and sent to the output terminal 1b. The constant impedance resistive attenuator 1 is a bridged T-type variable resistive attenuator. This constant impedance resistance attenuator 1 is equipped with PIN diodes 1c and 1d in its series arm and parallel arm, respectively, and a circuit for providing a DC bias voltage is connected in series by two coils 1f and 1g. A DC bias voltage is applied from a DC bias voltage generation circuit to a power supply terminal 1h which provides this DC bias voltage, and a control voltage is applied to a control terminal 1k which is a connection point between the two coils.
直流バイアス電圧発生回路は、定電流回路２に
より定電流があたえられたダイオード２と、その
端子電圧を増幅する増幅器４により構成される。
ダイオード２はその温度特性が定インピーダンス
抵抗減衰器１のPINダイオード１ｃおよび１ｄと
ほぼ等しいものが選ばれ、増幅器４はそのダイオ
ード３の端子電圧を２倍に増幅してバイアス電圧
とするように構成される。この２倍の値は、２個
のPINダイオード１ｃおよび１ｄが直流回路とし
ては直列に接続されているからである。 The DC bias voltage generation circuit includes a diode 2 to which a constant current is applied by a constant current circuit 2, and an amplifier 4 that amplifies the terminal voltage of the diode 2.
The diode 2 is selected so that its temperature characteristics are approximately equal to those of the PIN diodes 1c and 1d of the constant impedance resistance attenuator 1, and the amplifier 4 is configured to amplify the terminal voltage of the diode 3 by twice to use it as a bias voltage. be done. This double value is because the two PIN diodes 1c and 1d are connected in series as a DC circuit.
端子１ｋの制御電圧は、端子６に与えられる電
圧と、上記ダイオード３の端子電圧を利得可変増
幅器８で増幅した電圧とを、加算回路９で加算し
て与える。 The control voltage of the terminal 1k is obtained by adding the voltage applied to the terminal 6 and the voltage obtained by amplifying the terminal voltage of the diode 3 with a variable gain amplifier 8 in an adding circuit 9.
このように構成された回路では、端子６に与え
る電圧により端子１ｋの電圧が変化して、PINダ
イオード１ｃおよび１ｄの等化抵抗値が変化し、
端子１ａから端子１ｂに至る高周波信号の減衰量
が変化する。端子１ｈに与えられるバイアス電圧
は、この２個のPINダイオード１ｃおよび１ｄの
温度特性を補償するように、バイアス電圧発生回
路から与えられ、端子１ｋに与える制御電圧も増
幅器８から与えられる電圧により温度補償される
優れた回路である。 In the circuit configured in this way, the voltage applied to the terminal 6 changes the voltage at the terminal 1k, and the equalization resistance values of the PIN diodes 1c and 1d change.
The amount of attenuation of the high frequency signal from terminal 1a to terminal 1b changes. The bias voltage applied to the terminal 1h is applied from a bias voltage generation circuit so as to compensate for the temperature characteristics of these two PIN diodes 1c and 1d, and the control voltage applied to the terminal 1k is also applied to the temperature by the voltage applied from the amplifier 8. This is an excellent compensated circuit.
この回路の制御電圧に対する減衰量の特性を第
２図に示す。この第２図から分るように、この減
衰量の特性は減衰量が約4dBから約18dBまでは、
制御電圧に対してよい直線性を示すが、減衰量の
小さい範囲では直線性が悪い。すなわち、この回
路は約4dBの基本的な損失を与えないと、制御電
圧に対する減衰量の直線性が得られない欠点があ
る。 FIG. 2 shows the attenuation characteristics with respect to the control voltage of this circuit. As can be seen from Figure 2, the characteristics of this attenuation are as follows:
It shows good linearity with respect to the control voltage, but the linearity is poor in the range of small attenuation. That is, this circuit has the disadvantage that linearity of attenuation with respect to the control voltage cannot be obtained unless a basic loss of about 4 dB is provided.
本発明はこれを改良するもので、減衰量の小さ
い範囲でも制御電圧に対して減衰量の変化が直線
的である可変抵抗減衰回路を提供することを目的
とする。
The present invention improves this, and aims to provide a variable resistance attenuation circuit in which the attenuation changes linearly with respect to the control voltage even in a small attenuation range.
本発明は、上記加算回路の出力に第一の抵抗器
と、第二の抵抗器およびダイオードの直列回路と
で構成された分圧回路を備え、
上記制御電圧がこの分圧回路から与えられるよ
うに構成して、減衰量の変化特性を減衰量の小さ
い範囲まで拡大することを特徴とする。
The present invention includes a voltage divider circuit configured with a first resistor, a second resistor, and a series circuit of a diode at the output of the adder circuit, and the control voltage is applied from the voltage divider circuit. The attenuation amount change characteristic is expanded to a small attenuation amount range.
第３図は本発明第一実施例回路の構成図であ
る。定インピーダンス抵抗減衰器１の入力端子１
ａに与えられる高周波信号は、出力端子１ｂに減
衰を受けて現れる。この定インピーダンス抵抗減
衰器１は橋路Ｔ形の抵抗減衰器により構成され、
その直列アームおよび並列アームにはそれぞれ
PINダイオード１ｃおよび１ｄが挿入され、この
PINダイオード１ｃおよび１ｄには端子１ｈから
直流バイアス電圧が与えられている。このバイア
ス電圧は、定電流回路２で駆動されたダイオード
３の端子電圧を増幅器４で増幅することにより得
られ、PINダイオード１ｃおよび１ｄの温度特性
を補償するように構成されている。ダイオード３
はその温度特性がPINダイオード１ｃおよび１ｄ
とほぼ等しい特性のものが選ばれる。増幅器４
は、PINダイオード１ｃおよび１ｄが２個直列に
接続されているので、利得が２倍に設定される。
FIG. 3 is a block diagram of a circuit according to a first embodiment of the present invention. Input terminal 1 of constant impedance resistive attenuator 1
The high frequency signal applied to a is attenuated and appears at the output terminal 1b. This constant impedance resistance attenuator 1 is constituted by a bridge T-shaped resistance attenuator,
Its series and parallel arms each have
PIN diodes 1c and 1d are inserted and this
A DC bias voltage is applied to the PIN diodes 1c and 1d from a terminal 1h. This bias voltage is obtained by amplifying the terminal voltage of the diode 3 driven by the constant current circuit 2 with the amplifier 4, and is configured to compensate for the temperature characteristics of the PIN diodes 1c and 1d. diode 3
The temperature characteristics of PIN diodes 1c and 1d
The one with almost the same characteristics is selected. amplifier 4
Since two PIN diodes 1c and 1d are connected in series, the gain is set to double.
一方、定インピーダンス抵抗減衰器１のPINダ
イオード１ｃおよび１ｄには、コイル１ｆおよび
１ｇの接続点に接続された端子１ｋから制御電圧
が与えられる。この制御電圧は、端子６の電圧に
上記ダイオード３の端子電圧を増幅する増幅器８
の出力電圧を加算回路９で加算した電圧が与えら
れる。増幅器８は利得可変として、この利得を変
化させることにより、制御電圧の温度補償の効果
を加減する。 On the other hand, a control voltage is applied to the PIN diodes 1c and 1d of the constant impedance resistance attenuator 1 from a terminal 1k connected to the connection point of the coils 1f and 1g. This control voltage is applied to an amplifier 8 which amplifies the terminal voltage of the diode 3 to the voltage of the terminal 6.
A voltage obtained by adding the output voltages of 1 and 2 in an adder circuit 9 is given. The amplifier 8 has a variable gain, and by changing the gain, the temperature compensation effect of the control voltage is adjusted.
ここで本発明の特徴とするところは、加算回路
９の出力に、第一の抵抗器１１と、第二の抵抗器
１２およびダイオード１３の直列回路による分岐
回路を挿入し、定インピーダンス抵抗減衰器１の
制御電圧入力端子１ｋにはこの分岐回路の分岐電
圧を与えるように構成したところにある。このダ
イオード１３は、この例では、加算回路９の出力
電圧により順方向にバイアスされるように接続さ
れていて、加算回路９の出力電圧が約0.6Vにな
ると導通状態になる。すなわち、加算回路９の出
力電圧が0Vから0.6Vまでは、ダイオード１３は
開放状態であつて、加算回路９の出力電圧は抵抗
器１１を介して端子１ｋに与えられるが、この出
力電圧が0.6Vを越えると、ダイオード１３が導
通状態になり、抵抗器１１および１２による分岐
回路が作用して、その分岐電圧が端子１ｋに与え
られることになる。したがつて、第２図に示す制
御電圧に対する減衰量の特性は、制御電圧が約
0.6Vのところで折れ曲がり、全体の傾斜が緩や
かになつて制御電圧の低い範囲、すなわち減衰量
の小さい範囲からその直線性が良くなる。 Here, the feature of the present invention is that a branch circuit consisting of a series circuit of a first resistor 11, a second resistor 12, and a diode 13 is inserted into the output of the adder circuit 9, and a constant impedance resistance attenuator is inserted. The control voltage input terminal 1k of No. 1 is configured to receive the branch voltage of this branch circuit. In this example, the diode 13 is connected so as to be forward biased by the output voltage of the adder circuit 9, and becomes conductive when the output voltage of the adder circuit 9 reaches approximately 0.6V. That is, when the output voltage of the adder circuit 9 is from 0V to 0.6V, the diode 13 is in an open state, and the output voltage of the adder circuit 9 is applied to the terminal 1k via the resistor 11, but this output voltage is 0.6V. When the voltage exceeds V, the diode 13 becomes conductive, the branch circuit formed by the resistors 11 and 12 acts, and the branch voltage is applied to the terminal 1k. Therefore, the characteristics of the attenuation amount with respect to the control voltage shown in Fig. 2 are as follows:
It bends at 0.6V, the overall slope becomes gentle, and its linearity improves from the low control voltage range, that is, the small attenuation range.
第４図は本発明の第二実施例回路の構成図であ
る。この回路は上記第一実施例で説明した回路の
ダイオード１３に並列に、サーミスタ１４を接続
したところに特徴があり、その他の構成は上記第
一実施例と同様である。このサーミスタ１３の値
は抵抗器１１または１２の値よりかなり大きい値
が選ばれる。このサーミスタ１４はダイオード１
３が開放状態にあるとき、すなわち加算回路９の
出力電圧が低い範囲で作用し、この範囲で増幅器
８から与えられる電圧の温度補償の効果が薄くな
るところを補う効果がある。 FIG. 4 is a block diagram of a circuit according to a second embodiment of the present invention. This circuit is characterized in that a thermistor 14 is connected in parallel to the diode 13 of the circuit described in the first embodiment, and the other configurations are the same as in the first embodiment. The value of this thermistor 13 is chosen to be significantly larger than the value of resistor 11 or 12. This thermistor 14 is a diode 1
3 is in an open state, that is, in a range where the output voltage of the adder circuit 9 is low, and has the effect of compensating for the weakening of the temperature compensation effect of the voltage applied from the amplifier 8 in this range.
以上説明したように、本発明によれば、温度補
償特性の優れた定インピーダンス可変抵抗減衰回
路の特性を生かしながら、減衰量の小さい範囲か
ら制御電圧に対する減衰量の変化が直線的である
可変抵抗減衰回路が得られる。
As explained above, according to the present invention, while taking advantage of the characteristics of a constant impedance variable resistor attenuation circuit with excellent temperature compensation characteristics, a variable resistor whose attenuation changes linearly with respect to the control voltage from a small attenuation range A damping circuit is obtained.
第１図は改良前の回路の構成図。第２図は改良
前の回路の特性図。第３図は本発明実施例回路の
構成図。第４図は本発明第二の実施例回路の構成
図。
１…定インピーダンス抵抗減衰器、２…定電流
回路、３…温度特性がPINダイオードにほぼ等し
いダイオード、４…利得が２である増幅器、５…
電源、６…制御電圧を与える入力端子、８…利得
可変増幅器、９…加算回路、１１…第一の抵抗
器、１２…第二の抵抗器、１３…ダイオード、１
４…サーミスタ。
Figure 1 is a configuration diagram of the circuit before improvement. Figure 2 shows the characteristics of the circuit before improvement. FIG. 3 is a configuration diagram of a circuit according to an embodiment of the present invention. FIG. 4 is a configuration diagram of a circuit according to a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... constant impedance resistance attenuator, 2... constant current circuit, 3... diode whose temperature characteristics are almost equal to the PIN diode, 4... amplifier with gain of 2, 5...
Power supply, 6... Input terminal for giving control voltage, 8... Variable gain amplifier, 9... Adding circuit, 11... First resistor, 12... Second resistor, 13... Diode, 1
4...Thermistor.
Claims (1)
ンピーダンス抵抗減衰器を備え、 この定インピーダンス抵抗減衰器の直列アーム
および並列アームにそれぞれPINダイオードを含
み、 このPINダイオードの直流バイアス電圧は２つ
のPINダイオードについて直列に与えられるよう
に直流バイアス回路が構成され、 このPINダイオードの温度特性に対応するよう
に温度補償の施された上記直流バイアス電圧を発
生する直流バイアス電圧発生回路を備え、 上記２つのPINダイオードの直流回路の接続点
に上記定インピーダンス抵抗減衰器の減衰量を制
御するための制御電圧を与えるように構成され、 さらに、上記直流バイアス電圧発生回路の温度
補償の施された電圧を分岐して入力とする利得可
変増幅器と、 この利得可変増幅器の出力電圧を上記制御電圧
に加算する加算回路と を備えた温度補償型可変抵抗減衰回路において、 上記加算回路の出力に第一の抵抗器と、第二の
抵抗器およびダイオードの直列回路とで構成され
た分圧回路を備え、 上記制御電圧がこの分圧回路から与えられるよ
うに構成されたことを特徴とする温度補償型可変
抵抗減衰回路。[Claims] 1. A constant impedance resistor attenuator that attenuates an input high frequency signal and outputs the same, a PIN diode is included in each of the series arm and the parallel arm of the constant impedance resistor attenuator, and the DC bias of the PIN diode A DC bias circuit is configured so that voltage is applied in series to two PIN diodes, and a DC bias voltage generation circuit is used to generate the above DC bias voltage which is temperature compensated to correspond to the temperature characteristics of the PIN diodes. It is configured to apply a control voltage for controlling the amount of attenuation of the constant impedance resistor attenuator to the connection point of the DC circuit of the two PIN diodes, and further provides temperature compensation for the DC bias voltage generation circuit. In a temperature-compensated variable resistance attenuation circuit, the temperature-compensated variable resistance attenuation circuit is equipped with a variable gain amplifier that branches the output voltage as input, and an adder circuit that adds the output voltage of the variable gain amplifier to the control voltage. A temperature dividing circuit comprising a first resistor and a series circuit of a second resistor and a diode, and configured such that the control voltage is applied from the voltage dividing circuit. Compensated variable resistance attenuation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8969683A JPS59215108A (en) | 1983-05-20 | 1983-05-20 | Temperature compensation type variable resistance attenuation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8969683A JPS59215108A (en) | 1983-05-20 | 1983-05-20 | Temperature compensation type variable resistance attenuation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59215108A JPS59215108A (en) | 1984-12-05 |
| JPS646563B2 true JPS646563B2 (en) | 1989-02-03 |
Family
ID=13977925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8969683A Granted JPS59215108A (en) | 1983-05-20 | 1983-05-20 | Temperature compensation type variable resistance attenuation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59215108A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH675181A5 (en) * | 1988-05-19 | 1990-08-31 | Siemens Ag Albis | |
| KR20040013282A (en) * | 2002-08-05 | 2004-02-14 | 한국전자통신연구원 | Circuit for temperature compensation of attenuator and method thereof |
| KR100728756B1 (en) | 2004-10-14 | 2007-06-19 | 주식회사 이너트론 | Precision digital attenuator |
-
1983
- 1983-05-20 JP JP8969683A patent/JPS59215108A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59215108A (en) | 1984-12-05 |
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