JPS6457553U - - Google Patents
Info
- Publication number
- JPS6457553U JPS6457553U JP15294287U JP15294287U JPS6457553U JP S6457553 U JPS6457553 U JP S6457553U JP 15294287 U JP15294287 U JP 15294287U JP 15294287 U JP15294287 U JP 15294287U JP S6457553 U JPS6457553 U JP S6457553U
- Authority
- JP
- Japan
- Prior art keywords
- image
- pixels
- vertical
- original image
- addresses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010606 normalization Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案の一実施例に係わる画像正規化
回路の回路構成を示すブロツク図、第２図は従来
の正規化処理を説明するための図、第３図は文字
認識装置の基本的な回路構成を示すブロツク図、
第４図は上記文字認識装置の動作を説明するため
のフローチヤートである。
１……画像メモリ、２……垂直画素数検出器、
３……水平画素数検出器、５……記憶素子、６…
…アドレス発生器、７……正規化画素メモリ。
Fig. 1 is a block diagram showing the circuit configuration of an image normalization circuit according to an embodiment of the present invention, Fig. 2 is a diagram for explaining conventional normalization processing, and Fig. 3 is a basic diagram of a character recognition device. A block diagram showing the circuit configuration,
FIG. 4 is a flowchart for explaining the operation of the character recognition device. 1... Image memory, 2... Vertical pixel number detector,
3...Horizontal pixel number detector, 5...Storage element, 6...
...Address generator, 7...Normalized pixel memory.
Claims (1)
を予め設定された大きさの画像に正規化する正規
化回路において、入力される原画像の縦および横
方向の画素数と出力すべき正規化画像の縦および
横方向の位置とをアドレスとし、上記アドレスと
なつた上記正規化画像の画素となるべき上記原画
像の画素の縦および横方向の位置が予め記憶され
ている記憶素子を具備してなることを特徴とする
画像正規化回路。 In a normalization circuit that normalizes an original image cropped to an arbitrary size within a certain range to an image of a preset size, the number of pixels in the vertical and horizontal directions of the input original image and the number of pixels to be output are determined. The vertical and horizontal positions of the normalized image are taken as addresses, and a storage element is stored in advance in which the vertical and horizontal positions of the pixels of the original image that are to become the pixels of the normalized image that have become the addresses are stored. An image normalization circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15294287U JPS6457553U (en) | 1987-10-06 | 1987-10-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15294287U JPS6457553U (en) | 1987-10-06 | 1987-10-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6457553U true JPS6457553U (en) | 1989-04-10 |
Family
ID=31428328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15294287U Pending JPS6457553U (en) | 1987-10-06 | 1987-10-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6457553U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114176A (en) * | 1981-12-26 | 1983-07-07 | Fujitsu Ltd | Pattern recognizing device |
-
1987
- 1987-10-06 JP JP15294287U patent/JPS6457553U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114176A (en) * | 1981-12-26 | 1983-07-07 | Fujitsu Ltd | Pattern recognizing device |