JPS6455798A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To select a preliminary memory bit without fail by deciding the potential condition of a transistor connected to a setting input terminal while other edge of a fuse is connected to a source immediately after an address is fetched and holding this with an FF circuit. CONSTITUTION:To a setting input terminal S of an FF 17, the potential condition of a node N, namely, an H or L level is inputted by the cutting condition of fuses 1-6 of a redundant circuit and the potential condition is stably held. To an input terminal C, a setting clock signal SCK is inputted from a column address fetching signal 1CAS after a constant delaying time. From an output terminal Q and inversion Q, the output to hold the potential condition of the node N is inputted to the gate of transistors (TR) 14 and 15. The TR 14 and 15 are turned on and off in the condition of the H or L level of a clock signal CK and the gate inputted after the delaying time of the constant time from a row address fetching signal, and to the gate of a transistor for a transfer gate between an preliminary or ordinary memory bit line and a data line, a switching signal SCL or CL is sent.