JPS6455589A - Gray scale display device - Google Patents

Abstract

PURPOSE: To simplify constitution and to reduce cost by preparing a circuit for time-sequentially storing display data, converting the data into parallel data plural times and inverting the parallel data to a driving circuit together with an interface circuit necessary for driving. CONSTITUTION: A PLL circuit 101 generates a clock signal P synchronized with display signals R, G, B and a frequency division circuit 102 divides the frequency of the signal P. Output signals H, I are shifted by the period of the clock signal P and time-sequentially stored in latch circuits 104, 105 and outputted to a latch circuit 107. The circuit 107 simultaneously latches the stored data K1, K2 at the same timing by a delayed signal J and outputs display data L to be OD0 to OD2 and ED0 to ED2 of odd and even numbered driving data. An interface circuit 3 generates a counter output, a frame signal FRM, a latch signal LK, and a data shift lock signal SK necessary for driving. Thus display data can be simultaneously transferred by two systems OD to OD and ED to ED and a low speed driving circuit can be used.