JPS6455584A - Display controller - Google Patents

Display controller

Info

Publication number
JPS6455584A
JPS6455584A JP62211925A JP21192587A JPS6455584A JP S6455584 A JPS6455584 A JP S6455584A JP 62211925 A JP62211925 A JP 62211925A JP 21192587 A JP21192587 A JP 21192587A JP S6455584 A JPS6455584 A JP S6455584A
Authority
JP
Japan
Prior art keywords
signal
hsd
controlling
msl
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62211925A
Other languages
Japanese (ja)
Inventor
Yukio Ishiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62211925A priority Critical patent/JPS6455584A/en
Publication of JPS6455584A publication Critical patent/JPS6455584A/en
Pending legal-status Critical Current

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  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE: To prevent the edge disappearance of a display screen by providing the display controller with a control means for controlling the signal width of a synchronizing signal generated by a synchronizing signal generating circuit by an external signal. CONSTITUTION: An N output QHD corresponding to a reference signal. and an output DPD from a NOT gate 13 are inputted to a shift register 10 and the signals are sent from the QH and QF of the register 10 to a selector 11. The selector 11 receives an external signal MSL and sends a logic reset signal HRS. The signal HRS is converted into a control signal CHD for controlling the signal width of a horizontal synchronizing signal through a 2nd flip flop(FF) 7, a 3rd FF 8 and a NAND gate 9 and the signal CHD is converted into a horizontal synchronizing signal HSD through an AND gate 12. Thus time from the fall of the signal HSD up to the rise of a display signal KDP can be controlled by changing the width of the signal HSD by the signal MSL. Consequently the edge disappearance of a CRT screen can be corrected by controlling the signal MSL.
JP62211925A 1987-08-26 1987-08-26 Display controller Pending JPS6455584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62211925A JPS6455584A (en) 1987-08-26 1987-08-26 Display controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62211925A JPS6455584A (en) 1987-08-26 1987-08-26 Display controller

Publications (1)

Publication Number Publication Date
JPS6455584A true JPS6455584A (en) 1989-03-02

Family

ID=16613942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62211925A Pending JPS6455584A (en) 1987-08-26 1987-08-26 Display controller

Country Status (1)

Country Link
JP (1) JPS6455584A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110830742A (en) * 2019-12-02 2020-02-21 锐捷网络股份有限公司 Method and device for eliminating VGA signal jitter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110830742A (en) * 2019-12-02 2020-02-21 锐捷网络股份有限公司 Method and device for eliminating VGA signal jitter
CN110830742B (en) * 2019-12-02 2021-12-17 锐捷网络股份有限公司 Method and device for eliminating VGA signal jitter

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