JPS645492B2 - - Google Patents
Info
- Publication number
- JPS645492B2 JPS645492B2 JP58222751A JP22275183A JPS645492B2 JP S645492 B2 JPS645492 B2 JP S645492B2 JP 58222751 A JP58222751 A JP 58222751A JP 22275183 A JP22275183 A JP 22275183A JP S645492 B2 JPS645492 B2 JP S645492B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- error
- viterbi decoding
- original data
- decoding circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims 3
- 238000000605 extraction Methods 0.000 claims 2
- 230000006870 function Effects 0.000 claims 1
- 230000007704 transition Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 1
- IWBBKLMHAILHAR-UHFFFAOYSA-N chembl402341 Chemical compound C1=CC(O)=CC=C1C1=CC(=S)SS1 IWBBKLMHAILHAR-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Description
【発明の詳細な説明】
発明の技術分野
この発明は、たたみ込み符号を受信して誤り訂
正を行う誤り訂正回路に係り、特にビタビ復号回
路について回路規模ならびに消費電力の低減を可
能とした誤り訂正回路の構成に関するものであ
る。[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to an error correction circuit that receives convolutional codes and performs error correction, and in particular to an error correction circuit that enables reduction of circuit scale and power consumption in a Viterbi decoding circuit. This relates to the configuration of the circuit.
従来技術と問題点
ビタビ復号回路はたたみ込み符号に対して非常
に高い符号利得が得られる誤り訂正回路であり、
すでに衛星通信等の分野で一部実用化されてい
る。以下に従来のビタビ復号回路について説明す
る。Prior art and problems The Viterbi decoding circuit is an error correction circuit that can obtain a very high code gain compared to convolutional codes.
Parts of this technology have already been put into practical use in fields such as satellite communications. A conventional Viterbi decoding circuit will be explained below.
第１図にビタビ復号回路に対応する、たたみ込
み符号器の一例を示す。たたみ込み符号器は、Ｋ
段のシフトレジスタ１０５および排他的論理和１
０６，１０７から成り、入力をＢビツト、出力を
Ntビツトとした時、伝送効率Ｒ（Ｒ＝Ｂ／Nt）
のたたみ込み符号を生成する。第１図の例は拘束
長Ｋ（シフトレジスタ段数）＝３、Ｒ＝1/2の場合
を示している。 FIG. 1 shows an example of a convolutional encoder corresponding to a Viterbi decoding circuit. The convolutional encoder is K
stage shift register 105 and exclusive OR 1
Consists of 06,107, input is B bit, output is
When Nt bits, transmission efficiency R (R=B/Nt)
Generate a convolutional code for . The example in FIG. 1 shows a case where the constraint length K (number of shift register stages)=3 and R=1/2.
第２図に従来のビタビ復号回路の一例を示す。
図中２０１，２０２は受信たたみ込み符号入力端
子、２０３は加算比較選択（ACS）回路群を示
す。ACS回路群２０３の内部には図中ACS1〜
ACS4で示すNS＝2B FIG. 2 shows an example of a conventional Viterbi decoding circuit.
In the figure, 201 and 202 are reception convolutional code input terminals, and 203 is an addition comparison selection (ACS) circuit group. Inside the ACS circuit group 203, there are ACS 1 to ACS in the figure.
N S = 2 B in ACS 4
Claims (1)
系列を挿入されている受信信号から原データ系列
を主に復号する復号手段と、前記受信信号から誤
り系列を主に抽出する誤り抽出手段と、前記復号
手段によつて復号された原データ系列から前記誤
り抽出手段によつて抽出された誤り系列を除去す
る手段とを具えた誤り訂正回路によつて、受信し
たたたみ込み符号の誤り訂正を行う受信手段にお
いて、前記誤り訂正手段としてパスメモリ回路が
選択機能付きシフトレジスタで構成されるビタビ
復号回路を具え、該ビタビ復号回路において、該
ビタビ復号回路の生き残りパスの更新、記憶を行
う複数系列のパスメモリ回路のうちの特定の１系
列の最終ビツトを該ビタビ復号回路の出力として
取り出すとともに、該ビタビ復号回路のパスメモ
リ回路を原データ系列のたたみ込み符号の状態遷
移上前記特定の１系列の最終ビツトに関連を有す
る回路、および結線のみによつて構成したことを
特徴とする誤り訂正回路。1. A decoding means for mainly decoding an original data sequence from a received signal in which an error sequence has been inserted into an original data sequence consisting of a convolutional code; an error extraction means for mainly extracting an error sequence from the received signal; receiving means for correcting errors in the received convolutional code by means of an error correction circuit comprising means for removing the error sequence extracted by the error extraction means from the original data sequence decoded by the means; The path memory circuit as the error correction means includes a Viterbi decoding circuit constituted by a shift register with a selection function, and the Viterbi decoding circuit includes a plurality of series of path memories for updating and storing surviving paths of the Viterbi decoding circuit. The final bit of a specific series of circuits is taken out as the output of the Viterbi decoding circuit, and the path memory circuit of the Viterbi decoding circuit is used to extract the final bit of the specific series based on the state transition of the convolutional code of the original data series. What is claimed is: 1. An error correction circuit comprising only a circuit related to the above and connections.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58222751A JPS60114038A (en) | 1983-11-26 | 1983-11-26 | Error correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58222751A JPS60114038A (en) | 1983-11-26 | 1983-11-26 | Error correction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60114038A JPS60114038A (en) | 1985-06-20 |
| JPS645492B2 true JPS645492B2 (en) | 1989-01-31 |
Family
ID=16787334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58222751A Granted JPS60114038A (en) | 1983-11-26 | 1983-11-26 | Error correction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60114038A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5542440A (en) * | 1978-09-20 | 1980-03-25 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Decoding device for convolutional code |
-
1983
- 1983-11-26 JP JP58222751A patent/JPS60114038A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60114038A (en) | 1985-06-20 |
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