JPS645333B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for addressing operands used in control by a computer that does not have registers for storing operands, and in particular to a method for addressing operands included in instructions frequently used in one program. Regarding.

Recently, it has become common practice to control various devices using computers.

FIG. 1 is a block diagram showing a schematic configuration of such computer control, where 1 is a CPU (central processing unit: for example, 8085 or Z80) that does not have operand storage registers, and 2 is a ROM (read-only memory). ), 3 is a RAM (random access memory), 4 is an input port, and 5 is an output port.

In addition, 6 is the CPU1, ROM2, RAM3,
A common bus 10 connects the input port 4 and output port 5 to each other, and a common bus 10 connects the computer section (CPU 1, ROM
2, RAM 3, etc.) is the main body of the controlled device.

In such a configuration, the program for computer control of the device must be stored in advance in ROM2.
The information is stored in the memory, and is normally read out as needed to execute control.

When controlling a device, for example, it is possible to read the status of various input terminals of the controlled device from the input port, or conversely, output it to each part of the device from the output port to operate the corresponding output terminal. It is essential.

To this end, conventionally, a program for inputting and outputting each input terminal and output terminal was stored in a ROM in the form of pairs of operation codes and operands.

That is, for example, assuming that there are input terminals from #00 to #FE _H , for each input terminal, the OP code "IN" (read), the operand "input terminal number" (00 to FE _H ), and the read ( input)
The return instruction “RET” after completion was stored in the ROM.

An example of such a conventional program is
Using 8085CPU to input ports _0H to ^0FEH
Read data from 255 input ports and store in memory
Regarding the case of storing from 0 _H to 00FE _H , the third
As shown in the figure.

As the program progresses, each time it becomes necessary, these programs are called (or branched) to read input.

That is, in step 1 of Fig. 3, the first address of the storage memory is specified, and in step 2, the input port _{0H is} specified.
Read. In step 3, the read data is stored in the previously specified memory address _0H , and in step 4, the next storage destination is specified.

In subsequent steps, steps 2 to 4 described above
Repeat this operation until input port _0FEH has been read and stored in memory. As can be seen from FIG. 3, the required number of instruction bytes in this case is expressed as 3+(number of read ports-1)×4+3.

As a result, controlled equipment has become larger and more complex.
As the number of inputs and outputs increases, the number of program steps required to perform input and output increases.

In this case, the program is stored in the ROM, but the contents stored in the ROM cannot be rewritten or changed, and since this CPU8085 does not have registers for storing operands (the same applies to the Z80), the program can be stored in the ROM. Therefore, it is not possible to change the operands appropriately during the execution process.

For this reason, when reading or outputting data by accessing a large number of input/output terminals, the instructions to be executed for all input/output terminals and each input/output terminal must be [op code + operand]. ] It was necessary to define them one by one by the program.

Therefore, when the input/output terminals are changed due to design changes, etc., a complete correction of the program is required, resulting in a disadvantage that there is little flexibility and it is difficult to change the design.

Not only that, but it also had the disadvantage that it was not possible to shorten the program using so-called loop techniques.

The purpose of the present invention is to improve the drawbacks peculiar to CPUs that do not have registers for storing operands as described above, and to make it possible to use input/output ports similar to those equipped with registers for storing operands without using registers for storing operands. The object of the present invention is to provide a method of addressing operands that allows for flexibility in terms of changes, increases and decreases, and also allows for a reduction in the required amount of ROM if necessary.

In order to achieve the above object, the present invention focuses on the fact that the same type of operation code frequently appears, and stores an operation code (hereinafter referred to as OP) in RAM by a program stored in ROM. Execute the program stored in ROM by setting an area in advance to store the operand (abbreviated as code), and the return instruction (and return destination, if necessary) after executing that instruction. During the process, if necessary, the OP code of the instruction, the operand, and the return instruction (destination) after execution of the instruction are written to the setting area in the RAM, and the operand and/or
Or rewrite the return instruction so that it can be changed.

Next, an embodiment of the present invention will be described with reference to FIG.

Figure 2 is an example of using 8085CDU,
A in the figure shows a part of the program stored in the ROM 2, and B in FIG. 2 shows an example of storage area designation in the RAM 3. Furthermore, solid lines indicate data transfer, and points indicate program branches and returns.

First, program step 1001 in ROM 2 stores an input, in this example OP code "DB" (read), in an A register (not shown).
Program step 1002 reads the contents of the A register - that is, the OP code "DB" (read).
Write to OPCODE address in RAM3.

By program step 1003, the return method after executing the operation specified by the OP code "DB" - in this example, "C9" (return instruction) is stored in the A register. Program step 1004 sets the contents of the A register - that is, the return instruction after execution of the operation - in this example, "C9" - to (OPCODE
+2) Write to address.

As described above, an area for storing an OP code, an operand, and a return instruction after execution of the instruction is set in a specific area in the RAM 3. In other words, preparations for specifying and changing operands on the RAM 3 when there are multiple operands to be executed by the operation or instruction specified by the OP code are completed.

Assume that when the program progresses and reaches step 2001, the B register (not shown) has stored the number (for example, 01) of the input terminal from which the signal should be read due to the processing up to that point. . Program step 2001 transfers the contents of the B register - that is, the input terminal number (01) from which the signal is to be read - to the A register.

Program step 2002 writes the contents of the A register (ie, input end number 01) to the previously set OPRND address in RAM3. Then, in the next program step 2003, the instruction execution order is branched to the OPCODE address in RAM3.

Currently, the OP code “DB” (read) is stored at the OPCODE address in RAM3, so
Address 01 specified by the subsequent OPRND address data
The signal at the input end of is read. After this (read) command is executed, according to the return command “C9” stored at the next (OPCODE+2) address,
The program is a program step in ROM2.
Return to 2004.

Further processing progresses and the program step
Assume that when the input terminal 3001 is reached, the number of another input terminal (for example, 07) from which the signal should be read is stored in the B register. At this time, the program step
3001, the contents of the B register - that is, the input terminal number (07) from which the signal should be read - are transferred to the A register.

By the next program step 3002, the contents of the A register - the input terminal number (07) are calculated as before.
is stored in the OPRND address in RAM3 that was set earlier. Then, in program step 3003, the instruction execution order is branched to the OPCODE address in RAM3.

As a result, the signal from the input terminal numbered 07 is read in the same way as above, and the program is executed as follows.
In accordance with the return instruction specified by address (OPCODE+2) in RAM3, the program returns to program step 3004 in ROM2.

In addition, in the above example, the common operand (input terminal number) of the instructions was directly specified by the program in ROM.
Based on the operand stored in RAM, an operand that has a certain relationship with it (for example,
It is also possible to specify an address by storing an input number (input end of a number obtained by adding or subtracting a specific number to a stored input number) at an OPRND address in the RAM.

An example of a program for doing this is shown in FIG. This figure, similar to Figure 3, shows 8085CPU
is used to read data from 255 input ports from input port 0 _H to OFE _H , and from memory 0 _H.
This is an example of storing by _00FEH .

Steps 1 to 4 are steps 1001 to 1001 in FIG.
1004, a read instruction, operand, and return instruction are set and created in an appropriate area on the RAM. In step 5, the first address (here, address 0) of the storage memory is designated.

Steps 6 to 13 are a loop portion in which addresses of input ports on the RAM are sequentially rewritten and read repeatedly.

That is, in steps 6 and 7, the operand (input port address) is set and rewritten, and in step 8, a read instruction is executed. The read data is stored in the memory at the specified address in step 9, and the next storage destination is specified in step 10. Then, in steps 11 to 13, it is determined whether the iterative process has ended.

If loop processing is performed in this way, the number of required instruction bytes will be a constant value regardless of the number of reading ports (in the example in Figure 4, the total number of instruction bytes is 28, a fixed number), so In addition to achieving the same degree of freedom in changing input/output ports, increasing or decreasing input/output ports, it is also possible to shorten programs and reduce the required ROM capacity.

In addition, the types of OP codes to which the present invention is applied are:
The present invention is not limited to "read", but can be similarly applied to other OP codes such as output commands.

Furthermore, the return instruction is not limited to "C9" (return instruction) in the previous 8085CPU, but also "C3" with the return destination address as an operand.
(jump instruction), etc., and it is clear that in this way, the return destination after execution of this instruction can be changed in the same way.

As is clear from the above description, according to the present invention, an OP code, an operand, and a return instruction after executing the instruction specified by the OP code are stored in an address specified by a program in an area in RAM. The operands therein and/or the return instruction after instruction execution can be changed as appropriate by a program in the ROM.

To this end, according to the present invention, CPUs (such as Z80 and 8085) that do not have registers for storing operands
, as if you were using a CPU with registers for storing operands.
It becomes possible to freely change operands, return instructions after instruction execution, return destination, etc.

Therefore, the homogeneous
It is no longer necessary to prepare OP codes, return instructions, and return destinations in the program in ROM, which prevents programs from becoming longer and more complex, and reduces program occupancy.
This has the advantage that the capacity of the ROM can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of computer control, and FIG. 2 is a block diagram showing a schematic configuration of computer control.
A conceptual diagram showing an example of a program in ROM and a storage area setting in RAM, FIG. 3 is a diagram showing an example of a conventional program for a CPU that does not have registers for storing operands, and FIG. 4 is a diagram showing an example of a conventional program of the present invention. It is a figure which shows the example of a program by an Example. 1...CPU, 2...ROM, 3...RAM, 4
...Input port, 5...Output port, 10...Controlled device main body.

Claims (1)

[Scope of Claims] 1. A controlled device is connected to a computer section consisting of a central processing unit, a read-only memory, a random access memory, and a common bus that interconnects these, through an input port and an output port, and A method of addressing operands when the operation of control equipment is controlled by a computer section, and is used to store the operation code of a certain instruction, the operand, and the return instruction to the program in ROM after the instruction is executed. A program stored in the ROM provides an area in the RAM in advance, and a program stored in the ROM stores the operation code of the instruction, the operand, and the information after the instruction is executed in each of the areas.
A method for addressing an operand, characterized in that a return instruction to a program in a ROM is written, and the operand can be changed by a program stored in the ROM.