JPS6451882U - - Google Patents
Info
- Publication number
- JPS6451882U JPS6451882U JP14783387U JP14783387U JPS6451882U JP S6451882 U JPS6451882 U JP S6451882U JP 14783387 U JP14783387 U JP 14783387U JP 14783387 U JP14783387 U JP 14783387U JP S6451882 U JPS6451882 U JP S6451882U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- target data
- received
- threshold
- processing device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000013500 data storage Methods 0.000 description 1
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図はこの考案による信号処理装置の一実施
例の全体構成図、第２図はこの考案の動作説明図
、第３図は従来の信号処理装置の原理図である。
図において、１はデイジタル化ビデオ信号、２
は誤警確率一定回路、３はアンチログ回路、４は
第１のスレツシヨルド回路、５は第２のスレツシ
ヨルド回路、６はパルス幅検出回路、７はデータ
格納メモリ、１１は信号処理用の計算機である。
なお、図中同一符号は同一または相当部分を示す
。
FIG. 1 is an overall configuration diagram of an embodiment of a signal processing device according to this invention, FIG. 2 is an explanatory diagram of the operation of this invention, and FIG. 3 is a diagram showing the principle of a conventional signal processing device. In the figure, 1 is a digitized video signal, 2
is a constant false alarm probability circuit, 3 is an antilog circuit, 4 is a first threshold circuit, 5 is a second threshold circuit, 6 is a pulse width detection circuit, 7 is a data storage memory, and 11 is a signal processing computer. be.
Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ル化した受信ビデオ信号を２値化するスレツシヨ
ルド回路と、上記スレツシヨルド回路の出力を入
力し、目標以上の長さ（島、クラツタ等）の受信
信号を除去するパルス幅検出回路と、このパルス
幅検出回路で得られた受信ターゲツトデータを記
憶するメモリ回路とを２系統もつた回路系と、上
記２系統のメモリ回路の受信ターゲツトデータを
比較処理し、かつ上記各スレツシヨルド回路に対
し異なるスレツシヨルド値を設定し、１回の捜索
でスレツシヨルド値の異なるターゲツトデータを
取得できる機能を有する計算機とを備えた信号処
理装置。 In a signal processing device such as a radar, a threshold circuit that binarizes the digitized received video signal and a pulse that inputs the output of the threshold circuit and removes the received signal with a length longer than the target (islands, clutter, etc.) A circuit system having two systems including a width detection circuit and a memory circuit that stores the received target data obtained by the pulse width detection circuit, and a circuit system that compares and processes the received target data of the two systems of memory circuits, and A signal processing device comprising a computer having a function of setting different threshold values for a threshold circuit and acquiring target data with different threshold values in one search.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14783387U JPS6451882U (en) | 1987-09-28 | 1987-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14783387U JPS6451882U (en) | 1987-09-28 | 1987-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6451882U true JPS6451882U (en) | 1989-03-30 |
Family
ID=31418603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14783387U Pending JPS6451882U (en) | 1987-09-28 | 1987-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6451882U (en) |
-
1987
- 1987-09-28 JP JP14783387U patent/JPS6451882U/ja active Pending
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