JPS6448139A - Scan out control system - Google Patents

Scan out control system

Info

Publication number
JPS6448139A
JPS6448139A JP62205467A JP20546787A JPS6448139A JP S6448139 A JPS6448139 A JP S6448139A JP 62205467 A JP62205467 A JP 62205467A JP 20546787 A JP20546787 A JP 20546787A JP S6448139 A JPS6448139 A JP S6448139A
Authority
JP
Japan
Prior art keywords
scan out
data
control part
program
firm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62205467A
Other languages
Japanese (ja)
Inventor
Hiroshi Yonemasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62205467A priority Critical patent/JPS6448139A/en
Publication of JPS6448139A publication Critical patent/JPS6448139A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To report dummy scan out data to debug a program by reporting the value of data bits to the firm program instead of scan out data at the time of the test mode. CONSTITUTION:A scan out control part 5 refers to a flag bit 4-2 in a preliminarily stored scan out table 4, and the control part 5 reports a scan out address 4-1 to another data processor 2 and reads scan out data from a latch L1 or L3 to report it to a firm program 3 in case of the normal mode, and the control part 5 reports the value of data bits 4-3 to the firm program 3 as dummy scan out data to perform a prescribed processing in case of the test mode. Thus, prescribed processings are performed in order and debugging for these processings is possible even if the data processor 2 is not carried in yet.
JP62205467A 1987-08-19 1987-08-19 Scan out control system Pending JPS6448139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205467A JPS6448139A (en) 1987-08-19 1987-08-19 Scan out control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205467A JPS6448139A (en) 1987-08-19 1987-08-19 Scan out control system

Publications (1)

Publication Number Publication Date
JPS6448139A true JPS6448139A (en) 1989-02-22

Family

ID=16507346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205467A Pending JPS6448139A (en) 1987-08-19 1987-08-19 Scan out control system

Country Status (1)

Country Link
JP (1) JPS6448139A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07319727A (en) * 1994-02-04 1995-12-08 Sgs Thomson Microelectron Sa Digital processing circuit with test register

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07319727A (en) * 1994-02-04 1995-12-08 Sgs Thomson Microelectron Sa Digital processing circuit with test register

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