JPS6447050A - Manufacture of mos-type semiconductor device - Google Patents

Manufacture of mos-type semiconductor device

Info

Publication number
JPS6447050A
JPS6447050A JP20476187A JP20476187A JPS6447050A JP S6447050 A JPS6447050 A JP S6447050A JP 20476187 A JP20476187 A JP 20476187A JP 20476187 A JP20476187 A JP 20476187A JP S6447050 A JPS6447050 A JP S6447050A
Authority
JP
Japan
Prior art keywords
polycrystalline
concentration
rich
tisi2
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20476187A
Other languages
Japanese (ja)
Inventor
Makio Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP20476187A priority Critical patent/JPS6447050A/en
Publication of JPS6447050A publication Critical patent/JPS6447050A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a MOS-type semiconductor device with its sheet resistance low enough by a method wherein a metal-rich high-melting metal silicide layer is formed on a gate electrode and a high-concentration second conductivity type impurity diffusion layer, polycrystalline Si is deposited on the entire surface, and then metal-rich high-melting metal silicide is formed. CONSTITUTION:On a P-type Si substrate 101, an element isolating oxide film 102, a gate oxide film 103, a polycrystalline silicon gate electrode 104, a low- concentration N-type impurity diffusion layer 105, an insulating film side wall 106, and a high-concentration N-type impurity diffusion layer 107 are formed, in that order. Ti 108 is deposited on the entire surface by spattering and, after a short-period heat treatment, a Ti-rich silicide layer 109 is formed only on the polycrystalline silicon gate electrode 104 and source.drain 107. In a short- period heat treatment, the Ti-rich silicide layer 109 reacts with polycrystalline Si 110 for the formation of TiSi2 111. In this process, Si on the substrate side is slower than polycrystalline Si in reacting for the formation of TiSi2. Consumption is kept at the minimum of the substrate-side Si, which keeps high the impurity concentration along the TiSi2-Si interface.
JP20476187A 1987-08-18 1987-08-18 Manufacture of mos-type semiconductor device Pending JPS6447050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20476187A JPS6447050A (en) 1987-08-18 1987-08-18 Manufacture of mos-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20476187A JPS6447050A (en) 1987-08-18 1987-08-18 Manufacture of mos-type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6447050A true JPS6447050A (en) 1989-02-21

Family

ID=16495909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20476187A Pending JPS6447050A (en) 1987-08-18 1987-08-18 Manufacture of mos-type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6447050A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5958508A (en) * 1997-03-31 1999-09-28 Motorlola, Inc. Process for forming a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5958508A (en) * 1997-03-31 1999-09-28 Motorlola, Inc. Process for forming a semiconductor device

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