JPS6446845A - Simulation system for microcomputer - Google Patents

Simulation system for microcomputer

Info

Publication number
JPS6446845A
JPS6446845A JP62204389A JP20438987A JPS6446845A JP S6446845 A JPS6446845 A JP S6446845A JP 62204389 A JP62204389 A JP 62204389A JP 20438987 A JP20438987 A JP 20438987A JP S6446845 A JPS6446845 A JP S6446845A
Authority
JP
Japan
Prior art keywords
interruption
simulator
control
informs
delivers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62204389A
Other languages
Japanese (ja)
Inventor
Shigeru Mizuno
Yuji Tanaka
Hiroki Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Computer Engineering Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Computer Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Computer Engineering Co Ltd filed Critical Hitachi Ltd
Priority to JP62204389A priority Critical patent/JPS6446845A/en
Publication of JPS6446845A publication Critical patent/JPS6446845A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To detect the defect of a microcomputer program by simulating the interruption applied from an input/output device in a state approximate to that of a real device. CONSTITUTION:An interruption monitor mechanism 11 of a CPU simulator 1 delivers the interruption permitting information to an IO control simulator 2 as long as the interruption is possible. An interruption permission control mechanism 24 of the simulator 2 informs the interruption permission to an IO model 3 that delivered an interruption request. The model 3 sets an interruption type against the interruption request and returns the control to the mechanism 24. Thus the mechanism 24 informs the interruption type to the simulator 1 and an interruption execution control mechanism 12 of the simulator 1 checks the interruption types and delivers the control to the corresponding interruption routine. Thus the hardware interruption can be simulated in a state approximate to that of a real device. Then the defect of a microcomputer program can be detected.
JP62204389A 1987-08-18 1987-08-18 Simulation system for microcomputer Pending JPS6446845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62204389A JPS6446845A (en) 1987-08-18 1987-08-18 Simulation system for microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62204389A JPS6446845A (en) 1987-08-18 1987-08-18 Simulation system for microcomputer

Publications (1)

Publication Number Publication Date
JPS6446845A true JPS6446845A (en) 1989-02-21

Family

ID=16489727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62204389A Pending JPS6446845A (en) 1987-08-18 1987-08-18 Simulation system for microcomputer

Country Status (1)

Country Link
JP (1) JPS6446845A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01205347A (en) * 1988-02-01 1989-08-17 Internatl Business Mach Corp <Ibm> Method and apparatus for simulating i/o interrupt
JP2013210882A (en) * 2012-03-30 2013-10-10 Nec Soft Ltd Emulation device, emulation method, program, and development support system of built-in apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01205347A (en) * 1988-02-01 1989-08-17 Internatl Business Mach Corp <Ibm> Method and apparatus for simulating i/o interrupt
JP2013210882A (en) * 2012-03-30 2013-10-10 Nec Soft Ltd Emulation device, emulation method, program, and development support system of built-in apparatus

Similar Documents

Publication Publication Date Title
CA2225057A1 (en) Method and apparatus for testing software
EP0327196A3 (en) Processor simulation
ES2137476T3 (en) COMPUTER BASED TEACHING SYSTEM.
EP0191632A3 (en) Rom emulator for diagnostic tester
WO2002044650A3 (en) Method and apparatus for simulating the measurement of a part without using a physical measurement system
JPS6446845A (en) Simulation system for microcomputer
EP0327198A3 (en) Processor simulation
JPS56153457A (en) Measuring device for computer load
JPS57161953A (en) Simulating device for input and output device
McLaughlin Parallel implementation of a nonlinear real-time simulation technique.
Atlas MIxed level functional specification: A modeling methodology for computer system simulation.
JPS57176423A (en) Process simulating system
Korn Interactive simulation of dynamic systems and neural networks: A potent teaching tool.
JPS62190542A (en) Inspection system for input and output processor by simulator
KR860001193B1 (en) Address control system for software simulation
JPS54156449A (en) Simulate unit
JPS57712A (en) Decentralized train service control system
JPS55146555A (en) Simulation test device
Cheng exp 13 C-NMR Analysis of Multicomponent Polymer Systems
PITTS TPGITF user's manual(for computerized simulation by processors)
JPS55140130A (en) Testing method for train automatic operating apparatus
JPS5725051A (en) Address stop control system
Ellman Methods for Simulating Steady-State and Dynamic Behavior of Two-Way Cartridge Circuits
MILLS System modeling and simulation: Application of a research methodology and test[Ph. D.]
Liao et al. Investigation of time and intensity effects in operator workload and performance