JPS6446839A - Prolog processor - Google Patents
Prolog processorInfo
- Publication number
- JPS6446839A JPS6446839A JP20371187A JP20371187A JPS6446839A JP S6446839 A JPS6446839 A JP S6446839A JP 20371187 A JP20371187 A JP 20371187A JP 20371187 A JP20371187 A JP 20371187A JP S6446839 A JPS6446839 A JP S6446839A
- Authority
- JP
- Japan
- Prior art keywords
- goals
- pointer
- register
- local stack
- prolog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Devices For Executing Special Programs (AREA)
Abstract
PURPOSE:To simplify the prolog processing by securing such a constitution where an integrated access is always possible to a pointer pushed to a local stack with the offset applied to the present environment frame from the pointer (E register). CONSTITUTION:A main memory 1 is provided together with an instruction decoding part 2, a register file 3 and an arithmetic and logic unit ALU4. Then the continuation is applied to a local stack even when a paragraph contains just <=2 goals at a main body part when a paragraph including a cut goal is carried out. Thus an integrated access is always possible to a pointer pushed to the local stack with the offset given from an E register regardless of a fact whether the relevant paragraph contains a permanent variable or not, whether only a temporary variable is secured or not with >=2 pieces of goals of the main body part or whether the number of goals is equal to 2 or less. As a result, the prolog processing is simplified.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62203711A JP2590126B2 (en) | 1987-08-17 | 1987-08-17 | PROLOG processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62203711A JP2590126B2 (en) | 1987-08-17 | 1987-08-17 | PROLOG processing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6446839A true JPS6446839A (en) | 1989-02-21 |
JP2590126B2 JP2590126B2 (en) | 1997-03-12 |
Family
ID=16478584
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62203711A Expired - Lifetime JP2590126B2 (en) | 1987-08-17 | 1987-08-17 | PROLOG processing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2590126B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113760193A (en) * | 2021-08-26 | 2021-12-07 | 武汉天喻信息产业股份有限公司 | Data reading and writing method and device for resource-limited device and instruction set |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61213930A (en) * | 1985-03-19 | 1986-09-22 | Hitachi Ltd | Processing system for prolog language |
-
1987
- 1987-08-17 JP JP62203711A patent/JP2590126B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61213930A (en) * | 1985-03-19 | 1986-09-22 | Hitachi Ltd | Processing system for prolog language |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113760193A (en) * | 2021-08-26 | 2021-12-07 | 武汉天喻信息产业股份有限公司 | Data reading and writing method and device for resource-limited device and instruction set |
CN113760193B (en) * | 2021-08-26 | 2024-04-02 | 武汉天喻信息产业股份有限公司 | Data read-write method and device for resource-restricted device and instruction set |
Also Published As
Publication number | Publication date |
---|---|
JP2590126B2 (en) | 1997-03-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
RU96118491A (en) | DEVICE AND METHOD OF DATA PROCESSING USING TEAM SETS | |
EP0381469A3 (en) | Method and data processing unit for pipeline processing of register and register modifying specifiers within the same instruction | |
EP0768602A3 (en) | Variable word length VLIW-instruction processor | |
DE69230554D1 (en) | RISC MICROPROCESSOR ARCHITECTURE WITH FAST INTERRUPT AND EXCEPTION MODE | |
MY135426A (en) | Processor for executing highly efficient vliw | |
EP0213843A3 (en) | Digital processor control | |
EP0380849A3 (en) | Preprocessing implied specifiers in a pipelined processor | |
JPS6446839A (en) | Prolog processor | |
JPS55110348A (en) | Microprocessor | |
JPS55129855A (en) | Mode designation unit in electronic register | |
JPS56147246A (en) | Program control device | |
JPS6446838A (en) | Prolog processor | |
JPS5582357A (en) | Information processing unit | |
JPS56157538A (en) | Data processing system of advanced mode control | |
JPS6429934A (en) | Program execution control system | |
JPS57196350A (en) | Data processor | |
JPS5667453A (en) | Information processor with data generation part | |
JPS57105043A (en) | Address extension system | |
JPS5668878A (en) | Data processor | |
JPS5644942A (en) | Information processing unit | |
JPS641031A (en) | Data processor | |
JPS6446840A (en) | Prolog processor | |
JPS5629748A (en) | Microprogram control device | |
JPS55150041A (en) | Arithmetic processor | |
JPS6435630A (en) | Information processor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term | ||
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071205 Year of fee payment: 11 |