JPS6446793A - Display control system - Google Patents

Display control system

Info

Publication number
JPS6446793A
JPS6446793A JP62203109A JP20310987A JPS6446793A JP S6446793 A JPS6446793 A JP S6446793A JP 62203109 A JP62203109 A JP 62203109A JP 20310987 A JP20310987 A JP 20310987A JP S6446793 A JPS6446793 A JP S6446793A
Authority
JP
Japan
Prior art keywords
memory
display
data bus
video
display control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62203109A
Other languages
Japanese (ja)
Inventor
Hiroshi Wakabayashi
Yoshimichi Yahagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62203109A priority Critical patent/JPS6446793A/en
Publication of JPS6446793A publication Critical patent/JPS6446793A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE: To make it possible to simultaneously display video data stored in a video memory on two kinds of interface and timing display parts by using a dual port memory having a function to be driven independently of a memory access from a system bus. CONSTITUTION: The display control system is provided with the dual port memory 16 including a shift register for loading video data corresponding to one raster of a display screen in parallel by one data transfer access and then outputting the data to a serial data bus 17 synchronously with a shift clock. A video signal A6 from a display part A is read out by time-dividing the memory 16 by a character clock 10 generated from a display control circuit A9 and a video signal B19 from a display part B is read out by using the serial data bus 17 for the memory 16. Since a data bus 4 and the serial data bus 17 for the memory 16 can be independently driven, the two display parts A, B can be simultaneously displayed.
JP62203109A 1987-08-17 1987-08-17 Display control system Pending JPS6446793A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62203109A JPS6446793A (en) 1987-08-17 1987-08-17 Display control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62203109A JPS6446793A (en) 1987-08-17 1987-08-17 Display control system

Publications (1)

Publication Number Publication Date
JPS6446793A true JPS6446793A (en) 1989-02-21

Family

ID=16468544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62203109A Pending JPS6446793A (en) 1987-08-17 1987-08-17 Display control system

Country Status (1)

Country Link
JP (1) JPS6446793A (en)

Similar Documents

Publication Publication Date Title
EP0346437B1 (en) Apparatus for generating a cursor pattern on a display
EP0267612A3 (en) Timer/counter using a register block
EP0319661A3 (en) Source electrode driving circuit for matrix type liquid crystal display apparatus
CA2055724A1 (en) Mosaic picture display apparatus and external storage unit used therefor
EP0118255A3 (en) A graphic display unit
JPS5454531A (en) Crt display unti
JPS5768982A (en) Display device
JPS6446793A (en) Display control system
AU3475184A (en) High resolution video graphics system
JPS5644887A (en) Dot matrix electronic clock
GB2199678B (en) Pixel memory arrangement for information display system
JPS6446798A (en) Display control system
JPS6418193A (en) Matrix type display device
JPS6473890A (en) Color still picture transmitter
JPS57125875A (en) Electronic clock circuit
JPS6429926A (en) Fifo circuit
EP0318600A4 (en) Signal output device
JPS5765970A (en) Receiver for character broadcast
JPS54109331A (en) Character display unit
JPS6422182A (en) Method for driving active matrix type display
JPS5513412A (en) Display unit
JPS6480989A (en) Screen display
JPS642091A (en) Picture controller
JPS54154214A (en) Multi-character broadcast transmitter-receiver
JPS54137931A (en) Picture display unit