JPS6444720U - - Google Patents
Info
- Publication number
- JPS6444720U JPS6444720U JP1987139182U JP13918287U JPS6444720U JP S6444720 U JPS6444720 U JP S6444720U JP 1987139182 U JP1987139182 U JP 1987139182U JP 13918287 U JP13918287 U JP 13918287U JP S6444720 U JPS6444720 U JP S6444720U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- storage areas
- data
- same
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013500 data storage Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
図は本考案の一実施例を示すもので、第１図は
外観構成を示す正面図、第２図は電子回路の全体
の回路構成を示すブロツク図、第３図は第２図に
おけるチユーニング制御回路の詳細を示すブロツ
ク図、第４図は第３図におけるラストチヤンネル
記憶用メモリの詳細を示すブロツク図、第５図は
第４図における判断回路の詳細を示す図、第６図
は上記判断回路のタイミング信号を作成するタイ
ミング信号作成回路の構成を示すブロツク図、第
７図は上記ラストチヤンネル記憶用メモリに対す
る制御動作を説明するためのタイミングチヤート
である。
１…ケース、２…映像表示部、３…チヤンネル
表示部、４…ＬＣパネル、５ａ，５ｂ…アツプ／
ダウンキー、６…モードスイツチ、１１…チユー
ナ、１２…ＴＶリニア回路、１６…同期分離回路
、１７…チユーニング制御回路、１８…タイミン
グ制御回路、１９…ＡＦＴ制御回路、２１…キー
入力部、２３…チユーニング電圧作成回路、２４
…バンド切換回路、２５…Ａ／Ｄ変換回路、２８
…チヤンネル表示用ドライバ、３１…入力制御回
路、３２…チユーニングフロー制御回路、３３…
チヤンネルカウンタ、３４…チユーニング電圧記
憶用メモリ、３５…ラストチヤンネル記憶回路、
３６…チヤンネル表示信号作成回路、３７…同調
電圧カウンタ、３８…比較回路、３９…比較用カ
ウンタ、４２…バンド制御回路、４３…コンパレ
ータ、４４…コンパレータ、５１…同期検出回路
、６１…データ記憶用ＥＥＰＲＯＭ、６２…判断
回路、６３…アドレスカウンタ、６４…アドレス
記憶用ＥＥＰＲＯＭ、７１…ラツチ回路。
The figures show one embodiment of the present invention, in which Figure 1 is a front view showing the external configuration, Figure 2 is a block diagram showing the overall circuit configuration of the electronic circuit, and Figure 3 is the tuning control in Figure 2. 4 is a block diagram showing details of the last channel storage memory in FIG. 3, FIG. 5 is a block diagram showing details of the judgment circuit in FIG. 4, and FIG. 6 is a block diagram showing details of the judgment circuit in FIG. 4. FIG. 7 is a block diagram showing the configuration of a timing signal generation circuit that generates a timing signal for the circuit, and is a timing chart for explaining the control operation for the last channel storage memory. 1... Case, 2... Video display section, 3... Channel display section, 4... LC panel, 5a, 5b... Up/
Down key, 6...Mode switch, 11...Tuner, 12...TV linear circuit, 16...Sync separation circuit, 17...Tuning control circuit, 18...Timing control circuit, 19...AFT control circuit, 21...Key input section, 23... Tuning voltage generation circuit, 24
... Band switching circuit, 25 ... A/D conversion circuit, 28
...Channel display driver, 31...Input control circuit, 32...Tuning flow control circuit, 33...
Channel counter, 34... memory for tuning voltage storage, 35... last channel storage circuit,
36... Channel display signal creation circuit, 37... Tuning voltage counter, 38... Comparison circuit, 39... Comparison counter, 42... Band control circuit, 43... Comparator, 44... Comparator, 51... Synchronization detection circuit, 61... Data storage EEPROM, 62... Judgment circuit, 63... Address counter, 64... EEPROM for address storage, 71... Latch circuit.
Claims (1)
用の書換え可能な不揮発性メモリと、前記複数の
記憶領域の少なくとも２つの領域に同一のデータ
を書込む書込み手段と、前記少なくとも２つの記
憶領域のデータ読出し時にこの２つのデータが同
一であるか否かを判断する判断手段と、この判断
手段により２つのデータが同一でないと判断され
た際、前記少なくとも２の記憶領域を他の少なく
とも２つの記憶領域に切換える切換手段とを具備
したことを特徴とするチヤンネルデータ記憶装置
。 a rewritable non-volatile memory for storing channel data consisting of a plurality of storage areas; a writing means for writing the same data into at least two of the plurality of storage areas; and when reading data from the at least two storage areas. a determining means for determining whether the two data are the same; and when the determining means determines that the two data are not the same, switching the at least two storage areas to at least two other storage areas; A channel data storage device comprising a switching means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987139182U JPS6444720U (en) | 1987-09-11 | 1987-09-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987139182U JPS6444720U (en) | 1987-09-11 | 1987-09-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6444720U true JPS6444720U (en) | 1989-03-17 |
Family
ID=31402202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987139182U Pending JPS6444720U (en) | 1987-09-11 | 1987-09-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6444720U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5570997A (en) * | 1978-11-18 | 1980-05-28 | Nec Corp | Error bit check system for read only memory |
| JPS6226119A (en) * | 1985-07-29 | 1987-02-04 | Kanto Auto Works Ltd | Back window seal device for convertible car |
-
1987
- 1987-09-11 JP JP1987139182U patent/JPS6444720U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5570997A (en) * | 1978-11-18 | 1980-05-28 | Nec Corp | Error bit check system for read only memory |
| JPS6226119A (en) * | 1985-07-29 | 1987-02-04 | Kanto Auto Works Ltd | Back window seal device for convertible car |
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