JPS6444571A - Inter-processor coupling system - Google Patents

Abstract

PURPOSE:To improve coupling efficiency by coupling between the 1st and 2nd processors through an FIFO capable of shifting two or more data in a parallel state by the prescribed number of steps. CONSTITUTION:The FIFO memory 3 capable of shifting two 1-byte data in the parallel state by two steps is connected between the system bus 1A of the processor A and the system bus 1B of the processor B. A write control circuit 6A controls data writing from the processor A to writing side latches 4A, 5A and data writing from the latches 4A, 5A to the FIFO memory 3. A read control circuit 6B controls data reading from the FIFO memory 3 to reading side latches 4B, 5B, and when the latches 4B, 5B are emptied, two byte data are read out from an area pointed out by a reading pointer 7B and written in the latches 4B, 5B.