JPS6442485U - - Google Patents
Info
- Publication number
- JPS6442485U JPS6442485U JP13789287U JP13789287U JPS6442485U JP S6442485 U JPS6442485 U JP S6442485U JP 13789287 U JP13789287 U JP 13789287U JP 13789287 U JP13789287 U JP 13789287U JP S6442485 U JPS6442485 U JP S6442485U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output signal
- amplifier
- adder
- variable gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図はこの発明の一実施例を示すブロツク図
、第２図は従来のモノパルス追尾レーダ用受信機
を表わしたブロツク図、第３図は第２図を説明す
るための波形図である。
図において、１，２は可変利得ＩＦアンプ、２
，４はバンドパスフイルタ、５，６はＩＦアンプ
、７は位相検波器、８はビデオアンプ、９は加算
器、１０はローパスフイルタ、１１は差動アンプ
である。なお図中同一あるいは相当部分には同一
符号を付して示してある。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional monopulse tracking radar receiver, and FIG. 3 is a waveform diagram for explaining FIG. 2. In the figure, 1 and 2 are variable gain IF amplifiers, 2
, 4 are band pass filters, 5 and 6 are IF amplifiers, 7 is a phase detector, 8 is a video amplifier, 9 is an adder, 10 is a low pass filter, and 11 is a differential amplifier. In the drawings, the same or corresponding parts are denoted by the same reference numerals.
Claims (1)
得アンプと、この出力信号が入力されるバンドパ
スフイルタと、この出力信号が入力されるＩＦア
ンプと、この出力信号が入力され、２つの入力端
子を持つ位相検波器と、モノパルスレーダのΔ信
号が入力される可変利得アンプと、この出力信号
が入力されるバンドパスフイルタと、この出力信
号が入力され、その出力信号が上記位相検波器の
もう一つの入力端子へ接続されるＩＦアンプと、
上記位相検波器の出力信号が入力されるビデオア
ンプと、この出力信号が入力され、２つの入力端
子を持つ加算器と、この出力信号が入力されるロ
ーパスフイルタと、この出力信号が入力され、そ
の出力を上記加算器のもう一つの入力端子へ接続
している差動アンプで構成されたことを特長とす
るレーダ受信機。 A variable gain amplifier to which the Σ signal of the monopulse radar is input, a bandpass filter to which this output signal is input, an IF amplifier to which this output signal is input, and a variable gain amplifier to which this output signal is input, and has two input terminals. A phase detector, a variable gain amplifier to which the Δ signal of the monopulse radar is input, a bandpass filter to which this output signal is input, and a bandpass filter to which this output signal is input, and the output signal is input to another of the phase detectors. IF amplifier connected to the input terminal,
a video amplifier to which the output signal of the phase detector is input; an adder to which this output signal is input; and an adder having two input terminals; a low-pass filter to which this output signal is input; A radar receiver comprising a differential amplifier whose output is connected to another input terminal of the adder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13789287U JPS6442485U (en) | 1987-09-09 | 1987-09-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13789287U JPS6442485U (en) | 1987-09-09 | 1987-09-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6442485U true JPS6442485U (en) | 1989-03-14 |
Family
ID=31399731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13789287U Pending JPS6442485U (en) | 1987-09-09 | 1987-09-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6442485U (en) |
-
1987
- 1987-09-09 JP JP13789287U patent/JPS6442485U/ja active Pending
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