JPS6441001A - Multiplex digital controller - Google Patents
Multiplex digital controllerInfo
- Publication number
- JPS6441001A JPS6441001A JP19517987A JP19517987A JPS6441001A JP S6441001 A JPS6441001 A JP S6441001A JP 19517987 A JP19517987 A JP 19517987A JP 19517987 A JP19517987 A JP 19517987A JP S6441001 A JPS6441001 A JP S6441001A
- Authority
- JP
- Japan
- Prior art keywords
- pulses
- controller
- setting increase
- voltage
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Feedback Control In General (AREA)
Abstract
PURPOSE:To ensure the bumpless switch with high accuracy among plural controllers by converting the output of an AND circuit into the voltage value and supplying this voltage value to the controller of each system as a setting increase or decrease command. CONSTITUTION:The ANDs are calculated by AND circuits 16a-16d between a setting increase command given from a manual/automatic switch 3 and the high frequency pulses received from pulse generators 15a and 15b. Then the high frequency pulses are produced in proportion to the lengths of operation pulses 4a, 4b, 5a and 5b for a setting increase or decrease command. The pulse/ voltage converting circuits 17a and 17b converts these pulses into the analog voltage signals in response to the number of said pulses and decide the analog set value. Therefore the same control signal is obtained between A controller 8a and B controller 8b from the difference between said analog set value and a feedback signal 14. Thus the bumpless switch is possible with high accuracy between both controllers 8a and 8b.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19517987A JPS6441001A (en) | 1987-08-06 | 1987-08-06 | Multiplex digital controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19517987A JPS6441001A (en) | 1987-08-06 | 1987-08-06 | Multiplex digital controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6441001A true JPS6441001A (en) | 1989-02-13 |
Family
ID=16336764
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19517987A Pending JPS6441001A (en) | 1987-08-06 | 1987-08-06 | Multiplex digital controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6441001A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003018873A (en) * | 2001-06-29 | 2003-01-17 | Ishikawajima Harima Heavy Ind Co Ltd | Servo control equipment |
-
1987
- 1987-08-06 JP JP19517987A patent/JPS6441001A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003018873A (en) * | 2001-06-29 | 2003-01-17 | Ishikawajima Harima Heavy Ind Co Ltd | Servo control equipment |
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