JPS6439841A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPS6439841A
JPS6439841A JP19554587A JP19554587A JPS6439841A JP S6439841 A JPS6439841 A JP S6439841A JP 19554587 A JP19554587 A JP 19554587A JP 19554587 A JP19554587 A JP 19554587A JP S6439841 A JPS6439841 A JP S6439841A
Authority
JP
Japan
Prior art keywords
signal
outputted
information data
analog
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19554587A
Other languages
Japanese (ja)
Inventor
Yoshio Matsuzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP19554587A priority Critical patent/JPS6439841A/en
Publication of JPS6439841A publication Critical patent/JPS6439841A/en
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To contrive the improvement of the transmission efficiency by mixing a separated digital information data into a gap of an analog information data and transmitting it, by switching the separated digital information data and the analog information data. CONSTITUTION:A level detector 4 executes a level detection of an output of an AGC circuit 3, and when an analog signal AS is inputted, a control signal C outputted from a control part 5 becomes H and gates 6, 7 are switched, respectively, and the analog signal AS outputted from the AGC circuit 3 is transmitted. When the analog signal AS is not inputted, a start separator SS for showing a start of a digital signal data is added to the head of a digital signal DS reserved in a memory 8, and it is supplied to an encoder 10 and coding is executed. In this case, the control signal outputted from the control part 5 becomes L and the gates 6, 7 are switched, respectively, and the digital signal DS outputted from the encoder 10 is transmitted. In such a way, the transmission efficiency is improved.
JP19554587A 1987-08-05 1987-08-05 Data transmission system Pending JPS6439841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19554587A JPS6439841A (en) 1987-08-05 1987-08-05 Data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19554587A JPS6439841A (en) 1987-08-05 1987-08-05 Data transmission system

Publications (1)

Publication Number Publication Date
JPS6439841A true JPS6439841A (en) 1989-02-10

Family

ID=16342881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19554587A Pending JPS6439841A (en) 1987-08-05 1987-08-05 Data transmission system

Country Status (1)

Country Link
JP (1) JPS6439841A (en)

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