JPS6439123A - Error correcting circuit - Google Patents

Error correcting circuit

Info

Publication number
JPS6439123A
JPS6439123A JP19468887A JP19468887A JPS6439123A JP S6439123 A JPS6439123 A JP S6439123A JP 19468887 A JP19468887 A JP 19468887A JP 19468887 A JP19468887 A JP 19468887A JP S6439123 A JPS6439123 A JP S6439123A
Authority
JP
Japan
Prior art keywords
bits
decoder
error
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19468887A
Other languages
Japanese (ja)
Inventor
Shigeo Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19468887A priority Critical patent/JPS6439123A/en
Publication of JPS6439123A publication Critical patent/JPS6439123A/en
Pending legal-status Critical Current

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  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To realize the function of an error position reference table by using a decoder which defines the residue signal of a division circuit as its input and switching the connections to secure the correspondence between the output of the decoder and a bit position where an error should be corrected. CONSTITUTION:N and A are defined as a positive integer of >=2 and a positive integer of >=1 respectively. The block bit length of a single block of a code is set at (2N-1-A) bits or (2N-A) bits together with the information bit length within said single block is set at (2N-1-A-N) bits. Then the BCH code or the humming code that is encoded by means of an N-degree generating polynomial is defined as an input signal. The residue signal consisting of N bits obtained by dividing said input signal by the frequency equal to said block bit length with use of said polynomial is supplied to a decoder 16 having its input of N bits and output of 2N bits or (2N-1) bits. Then the output of this decoder is used as the error bit position data of said input signal.
JP19468887A 1987-08-04 1987-08-04 Error correcting circuit Pending JPS6439123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19468887A JPS6439123A (en) 1987-08-04 1987-08-04 Error correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19468887A JPS6439123A (en) 1987-08-04 1987-08-04 Error correcting circuit

Publications (1)

Publication Number Publication Date
JPS6439123A true JPS6439123A (en) 1989-02-09

Family

ID=16328628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19468887A Pending JPS6439123A (en) 1987-08-04 1987-08-04 Error correcting circuit

Country Status (1)

Country Link
JP (1) JPS6439123A (en)

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