JPS6438830A - Adder - Google Patents
AdderInfo
- Publication number
- JPS6438830A JPS6438830A JP19587787A JP19587787A JPS6438830A JP S6438830 A JPS6438830 A JP S6438830A JP 19587787 A JP19587787 A JP 19587787A JP 19587787 A JP19587787 A JP 19587787A JP S6438830 A JPS6438830 A JP S6438830A
- Authority
- JP
- Japan
- Prior art keywords
- bits
- data
- addition
- module
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To quickly generate the final result of shift operation by outputting upper bits resulting from addition of upper bits of addition data as partial shift data. CONSTITUTION:Each module outputs corresponding one of signals UG1-UG3, which indicates success of the condition that carry C63 generated in lower eight bits by inputted addition data a0-63 and b0-63 is transmitted up to the weight position of the fourth bit from the most significant bit, to the just higher-order module. Each module reports corresponding one of signals UP1-UP3, which indicates success of the condition that carry is transmitted up to the weight position of the fourth bit from the least significant bit, to the just higher-order module. Only upper eight bits of inputted addition data are added, and data corresponding to upper four bits of the addition result is generated as partial shift data and is transferred to the just higher-order module as R16-19, R32-35, and R48-51.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19587787A JP2508118B2 (en) | 1987-08-05 | 1987-08-05 | Adder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19587787A JP2508118B2 (en) | 1987-08-05 | 1987-08-05 | Adder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6438830A true JPS6438830A (en) | 1989-02-09 |
| JP2508118B2 JP2508118B2 (en) | 1996-06-19 |
Family
ID=16348471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19587787A Expired - Lifetime JP2508118B2 (en) | 1987-08-05 | 1987-08-05 | Adder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2508118B2 (en) |
-
1987
- 1987-08-05 JP JP19587787A patent/JP2508118B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2508118B2 (en) | 1996-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0449265A3 (en) | Random number generator | |
| EP0366938A3 (en) | High speed switch as for an optical communication system | |
| EP0103722A3 (en) | Multiplying circuit | |
| EP0248166A3 (en) | Binary multibit multiplier | |
| CA2132756A1 (en) | High Efficiency Learning Network | |
| EP0308844A3 (en) | Phase shift circuit | |
| JPS6438830A (en) | Adder | |
| AU6831696A (en) | Apparatus for use as an educational toy | |
| GB2187013A (en) | Digital companding circuit | |
| JPS57186897A (en) | Loudspeaker | |
| CA2024362A1 (en) | Transmitting power control circuit | |
| JPS53129925A (en) | Memory device | |
| CA2131880A1 (en) | Vector Quantizer | |
| EP0291963A3 (en) | Fast c-mos adder | |
| EP0279419A3 (en) | Image signal binary encoder | |
| JPS56115967A (en) | Scan converter | |
| NZ330670A (en) | Processing optical digital signal, by modifying at least one bit in n-bit optical signal | |
| JPS6484331A (en) | Absolute value circuit | |
| JPS56146338A (en) | Translating system of alarm signal | |
| JPS57132442A (en) | Pcm signal compression circuit | |
| JPS5666977A (en) | Picture gradation property conversion device | |
| AU2003230094A1 (en) | Data acquisition system | |
| JPS5745642A (en) | Bit processing method for microcomputer | |
| EP0292854A3 (en) | C-mos arithmetic-logic unit | |
| SU696539A1 (en) | Matrix decoder for combination switch |