JPS6438693U - - Google Patents

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Publication number
JPS6438693U
JPS6438693U JP9330188U JP9330188U JPS6438693U JP S6438693 U JPS6438693 U JP S6438693U JP 9330188 U JP9330188 U JP 9330188U JP 9330188 U JP9330188 U JP 9330188U JP S6438693 U JPS6438693 U JP S6438693U
Authority
JP
Japan
Prior art keywords
series circuit
operational amplifier
mos transistor
liquid crystal
variable resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9330188U
Other languages
Japanese (ja)
Other versions
JPH0228552Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988093301U priority Critical patent/JPH0228552Y2/ja
Publication of JPS6438693U publication Critical patent/JPS6438693U/ja
Application granted granted Critical
Publication of JPH0228552Y2 publication Critical patent/JPH0228552Y2/ja
Expired legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは液晶のコントラスト対印加実効電圧
特性を示すグラフ。第1図bは、Vth、Vsa
t、Voffの温度特性を表わすグラフ。第1図
cは液晶表示体への印加電圧波形の一例。第2図
は液晶表示体用電源の従来構成の一例。第3図は
本考案の液晶表示体用安定化電源の構成例。第4
図a,b,c,d,eは第3図における温度係数
、電圧レベル調整回路の説明図。第5図aは第3
図における入力オフセツト電圧が零の演算増幅器
の構成例。第5図bは第3図における基準電圧源
内蔵の演算増幅器。第6図は第3図におけるNP
Nトランジスタの構造を示す図。
FIG. 1a is a graph showing the contrast versus applied effective voltage characteristics of a liquid crystal. Figure 1b shows Vth, Vsa
Graph showing temperature characteristics of t and Voff. Figure 1c shows an example of the voltage waveform applied to the liquid crystal display. Figure 2 shows an example of a conventional configuration of a power supply for a liquid crystal display. FIG. 3 shows an example of the configuration of the stabilized power supply for liquid crystal display according to the present invention. Fourth
Figures a, b, c, d, and e are explanatory diagrams of the temperature coefficient and voltage level adjustment circuits in Figure 3. Figure 5 a is the third
An example of the configuration of an operational amplifier in which the input offset voltage in the figure is zero. FIG. 5b shows the operational amplifier with a built-in reference voltage source in FIG. 3. Figure 6 shows the NP in Figure 3.
A diagram showing the structure of an N transistor.

補正 昭63.8.12 実用新案登録請求の範囲を次のように補正する
Amendment August 12, 1983 The scope of claims for utility model registration is amended as follows.

【実用新案登録請求の範囲】 液晶表示体に該液晶表示体の温度特性を補償し
た電源電圧を供給する液晶表示体用安定化電源に
於いて、PN接合ダイオード、第1の可変抵抗及
び第1のMOSトランジスタを電源間に直列接続
して成る第1の直列回路と、2入力の少なくとも
一方を該第1の直列回路に接続すると共に該2入
力間に温度に対して安定な基準電圧を有し、出力
を前記第1のMOSトランジスタのゲートに供給
して前記第1の直列回路に定電流を流せしめるC
MOS型の第1の演算増幅器と、第2の可変抵抗
及び第2のMOSトランジスタを前記電源間に直
列接続して成る第2の直列回路と、前記第1及び
第2の可変抵抗からの選択された電位を第1入力
及び第2入力に各々入力すると共に出力を前記第
2のMOSトランジスタのゲートに供給するCM
OS型の第2の演算増幅器とを備え、前記第1の
可変抵抗と前記第2の可変抵抗の少なくとも一方
は、複数の分割点と、該分割点の各々と前記第2
の演算増幅器の入力との間に接続されて一つが導
通状態に設定される複数のMOSトランジスタス
イツチと、初期調整時に該複数のMOSトランジ
スタスイツチに設定された導通状態を記憶してそ
の導通状態を維持せしめる不揮発性記憶装置とを
具備すること
を特徴とする液晶表示体用安定化電
源。 図面の簡単な説明を次のように補正する。 明細書第13頁12行目及び13行目の「の一
例。」とあるを「を示す図。」と補正する。 明細書第13頁14行目〜15行目、19行目
「構成例。」とあるを「構成を示す図。」と補正
する。 明細書第14頁2行目「増幅器。」とあるを「
増幅器を示す図。」と補正する。
[Scope of Claim for Utility Model Registration] In a stabilized power supply for a liquid crystal display that supplies a power supply voltage that compensates for the temperature characteristics of the liquid crystal display to a liquid crystal display, a PN junction diode, a first variable resistor, and a first a first series circuit comprising MOS transistors connected in series between power supplies; at least one of two inputs is connected to the first series circuit; and a temperature-stable reference voltage is provided between the two inputs. and a C supplying an output to the gate of the first MOS transistor to cause a constant current to flow through the first series circuit.
a second series circuit formed by connecting a first MOS operational amplifier, a second variable resistor, and a second MOS transistor in series between the power supplies; and a selection from the first and second variable resistors. a CM that inputs the potentials at the first input and the second input, respectively, and supplies the output to the gate of the second MOS transistor;
an OS-type second operational amplifier, and at least one of the first variable resistor and the second variable resistor has a plurality of division points, and each of the division points and the second
A plurality of MOS transistor switches connected between the input of an operational amplifier and one of which is set to a conductive state, and a conductive state set to the plurality of MOS transistor switches at the time of initial adjustment are memorized and the conductive state is determined. 1. A stabilized power supply for a liquid crystal display, comprising a nonvolatile memory device for maintaining the power . The brief description of the drawing has been amended as follows. On page 13, lines 12 and 13 of the specification, the words "an example." are corrected to "a figure showing." On page 13 of the specification, lines 14 to 15 and 19, the words ``Example of configuration.'' are corrected to ``Diagrams showing the configuration.'' On page 14 of the specification, line 2, replace “Amplifier.” with “
A diagram showing an amplifier. ” he corrected.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 液晶表示体に該液晶表示体の温度特性を補償し
た電源電圧を供給する液晶表示体用安定化電源に
於いて、PN接合ダイオード、第1の可変抵抗及
び第1のMOSトランジスタを電源間に直列接続
して成る第1の直列回路と、2入力の少なくとも
一方を該第1の直列回路に接続すると共に該2入
力間に温度に対して安定な基準電圧を有し、出力
を前記第1のMOSトランジスタのゲートに供給
して前記第1の直列回路に定電流を流せしめるC
MOS型の第1の演算増幅器と、第2の可変抵抗
及び第2のMOSトランジスタを前記電源間に直
列接続して成る第2の直列回路と、前記第1及び
第2の可変抵抗からの選択された電位を第1入力
及び第2入力に各々入力すると共に出力を前記第
2のMOSトランジスタのゲートに供給するCM
OS型の第2の演算増幅器とを備え、前記第1の
可変抵抗と前記第2の可変抵抗の少なくとも一方
は、複数の分割点と、該分割点の各々と前記第2
の演算増幅器の入力との間に接続されて一つが導
通状態に設定される複数のMOSトランジスタス
イツチとを具備して成り前記PN接合ダイオード
、前記第1の演算増幅器及び前記第2の演算増幅
器と共に同一基板上に集積化されることを特徴と
する液晶表示体用安定化電源。
In a stabilized power supply for a liquid crystal display that supplies a power supply voltage that compensates for the temperature characteristics of the liquid crystal display, a PN junction diode, a first variable resistor, and a first MOS transistor are connected in series between the power supplies. a first series circuit connected to the first series circuit; at least one of two inputs is connected to the first series circuit, and a reference voltage stable with respect to temperature is provided between the two inputs, and an output is connected to the first series circuit; C supplied to the gate of the MOS transistor to cause a constant current to flow through the first series circuit;
a second series circuit formed by connecting a first MOS operational amplifier, a second variable resistor, and a second MOS transistor in series between the power supplies; and a selection from the first and second variable resistors. a CM that inputs the potentials at the first input and the second input, respectively, and supplies the output to the gate of the second MOS transistor;
an OS-type second operational amplifier, and at least one of the first variable resistor and the second variable resistor has a plurality of division points, and each of the division points and the second
a plurality of MOS transistor switches connected between the input of the operational amplifier and one of which is set to a conductive state, together with the PN junction diode, the first operational amplifier, and the second operational amplifier. A stabilized power supply for a liquid crystal display characterized by being integrated on the same substrate.
JP1988093301U 1988-07-14 1988-07-14 Expired JPH0228552Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988093301U JPH0228552Y2 (en) 1988-07-14 1988-07-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988093301U JPH0228552Y2 (en) 1988-07-14 1988-07-14

Publications (2)

Publication Number Publication Date
JPS6438693U true JPS6438693U (en) 1989-03-08
JPH0228552Y2 JPH0228552Y2 (en) 1990-07-31

Family

ID=31317747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988093301U Expired JPH0228552Y2 (en) 1988-07-14 1988-07-14

Country Status (1)

Country Link
JP (1) JPH0228552Y2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5197361A (en) * 1975-02-21 1976-08-26
JPS54133896A (en) * 1978-04-10 1979-10-17 Hitachi Ltd Compensator circuit for temperature of liquid-crystal driver
JPS54144195A (en) * 1978-05-02 1979-11-10 Seiko Epson Corp Electronic unit with liquid crystal display unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5197361A (en) * 1975-02-21 1976-08-26
JPS54133896A (en) * 1978-04-10 1979-10-17 Hitachi Ltd Compensator circuit for temperature of liquid-crystal driver
JPS54144195A (en) * 1978-05-02 1979-11-10 Seiko Epson Corp Electronic unit with liquid crystal display unit

Also Published As

Publication number Publication date
JPH0228552Y2 (en) 1990-07-31

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