JPS6437034A - Standard cell - Google Patents

Standard cell

Info

Publication number
JPS6437034A
JPS6437034A JP19352787A JP19352787A JPS6437034A JP S6437034 A JPS6437034 A JP S6437034A JP 19352787 A JP19352787 A JP 19352787A JP 19352787 A JP19352787 A JP 19352787A JP S6437034 A JPS6437034 A JP S6437034A
Authority
JP
Japan
Prior art keywords
lines
cell
extended
lateral direction
standard cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19352787A
Other languages
Japanese (ja)
Inventor
Katsuhiko Aisu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP19352787A priority Critical patent/JPS6437034A/en
Publication of JPS6437034A publication Critical patent/JPS6437034A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive to secure the current capacities of power lines and to contrive to prevent an error due to a wiring resistance from being included by a method wherein electronic circuits peculiar to each standard cell are respec tively constituted within a region of a constant height and the power lines, which are extended in the lateral direction, are provided three lines or more. CONSTITUTION:A power line 6, which is extended in the lateral direction along the lower side of a standard cell 14, is provided, a power line 8, which is extended in the lateral direction along the upper side of the cell 14, is provided and moreover, a third power line 16, which is extended in the lateral direction, is provided in the central part of the cell 14 as well. The height H of the cell 14 is constant and electronic circuits peculiar to each standard cell 14 are respec tively constituted at the region between the lines 6 and 16 and the region be tween the lines 8 and 16. Thereby, it becomes possible to provide a wiring of a desirable width, a sufficient current capacity can be secured for the power lines and moreover, even in case a reference voltage is supplied, an error due to a wiring resistance can be eliminated.
JP19352787A 1987-08-01 1987-08-01 Standard cell Pending JPS6437034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19352787A JPS6437034A (en) 1987-08-01 1987-08-01 Standard cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19352787A JPS6437034A (en) 1987-08-01 1987-08-01 Standard cell

Publications (1)

Publication Number Publication Date
JPS6437034A true JPS6437034A (en) 1989-02-07

Family

ID=16309556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19352787A Pending JPS6437034A (en) 1987-08-01 1987-08-01 Standard cell

Country Status (1)

Country Link
JP (1) JPS6437034A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH029149A (en) * 1988-06-28 1990-01-12 Toshiba Corp Standard cell

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198843A (en) * 1984-03-23 1985-10-08 Fujitsu Ltd Master slice approach integrated circuit
JPS61230334A (en) * 1985-04-05 1986-10-14 Nec Corp Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198843A (en) * 1984-03-23 1985-10-08 Fujitsu Ltd Master slice approach integrated circuit
JPS61230334A (en) * 1985-04-05 1986-10-14 Nec Corp Semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH029149A (en) * 1988-06-28 1990-01-12 Toshiba Corp Standard cell
US5401988A (en) * 1988-06-28 1995-03-28 Kabushiki Kaisha Toshiba Standard cell layout arrangement for an LSI circuit

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