JPS6436149A - Packet multiplexing system - Google Patents

Packet multiplexing system

Info

Publication number
JPS6436149A
JPS6436149A JP62191178A JP19117887A JPS6436149A JP S6436149 A JPS6436149 A JP S6436149A JP 62191178 A JP62191178 A JP 62191178A JP 19117887 A JP19117887 A JP 19117887A JP S6436149 A JPS6436149 A JP S6436149A
Authority
JP
Japan
Prior art keywords
packet
data bus
data
communication procedure
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62191178A
Other languages
Japanese (ja)
Inventor
Kazuo Tsuzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62191178A priority Critical patent/JPS6436149A/en
Publication of JPS6436149A publication Critical patent/JPS6436149A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain high speed packet multiplexing by providing a reception packet FIFO memory and a transmission packet FIFO memory between a data communication procedure controller and a data bus and using the hardware so as to manage the packet buffer memory. CONSTITUTION:Reception packet FIFO memories 21-2n and transmission packet FIFO memories 31-3n are provided between data communication procedure controller 11-1n and a data bus 6 respectively to transfer packet data with the packet buffer memory 4 via the data bus in the unit of packets as a badge job. Moreover, a packet buffer management controller 5 transmits/receives a packet transfer control signal with the data communication procedure controllers 11-1n to allow the hardware to manage the packet buffer memory 4. Thus, the number of times of data bus access contention is less and high speed packet multiplexing is attained.
JP62191178A 1987-07-30 1987-07-30 Packet multiplexing system Pending JPS6436149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62191178A JPS6436149A (en) 1987-07-30 1987-07-30 Packet multiplexing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62191178A JPS6436149A (en) 1987-07-30 1987-07-30 Packet multiplexing system

Publications (1)

Publication Number Publication Date
JPS6436149A true JPS6436149A (en) 1989-02-07

Family

ID=16270198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62191178A Pending JPS6436149A (en) 1987-07-30 1987-07-30 Packet multiplexing system

Country Status (1)

Country Link
JP (1) JPS6436149A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5839914A (en) * 1995-05-22 1998-11-24 Yazaki Corporation Connector for detecting incomplete insertion of terminal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5839914A (en) * 1995-05-22 1998-11-24 Yazaki Corporation Connector for detecting incomplete insertion of terminal

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