JPS6435488U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the hardware configuration according to an embodiment of the present invention, and FIG. 2 is a flowchart showing the processing functions and procedures of the above embodiment. 1... Communication interface, 2... Matrix calculation device, 3... Comparison device, 4... Set value output device, 5... Abnormal signal detection device, 6... Output processing device, 7... Display device, S ₁ ...signal input function, _S2 ...error _{calculation function, S3...error vector configuration function, S4...norm-based diagnosis function, S5 ... norm} minimum value detection function, _S6 ...norm minimum Minimum value export function, _S7 ...Display function.

Claims (1)

[Scope of utility model registration request] The norm of the error vector is calculated by substituting multiple signals emitted from an instrumentation system such as a plant into a nonlinear or linear simultaneous equation that represents the physical cause-and-effect relationship that should be established between each signal, and from the calculation results obtained. It is a device that determines the presence or absence of a failure based on its size, and when it is determined that there is a failure, the element that minimizes the norm of the error vector when one of the elements of the column vector of the above simultaneous equations is varied. A failure detection device characterized by detecting and determining that there is an abnormality in a detection signal corresponding to this element.