JPS6435401U

JPS6435401U -

Info

Publication number: JPS6435401U
Application number: JP5674787U
Authority: JP
Priority date: 1987-04-16
Filing date: 1987-04-16
Publication date: 1989-03-03

Description

[Brief explanation of the drawing]

第１図は本考案の実施例を示す構成図、第２図
はその動作説明図、第３図、第４は従来技術の一
例を示す構成図、第５図はその動作説明図である
。１……調節計、２，３……指示計、４……第１
スイツチ手段、５……制御弁、７，８，９……第
２、第３、第４スイツチ手段、１０，１１，１２
……第１、第２、第３加算手段、１３，１４……
第１、第２フイルタ手段、１５，１６……第１、
第２シーケンス回路。 FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram explaining its operation, FIGS. 3 and 4 are block diagrams showing an example of the prior art, and FIG. 5 is a diagram explaining its operation. 1... Controller, 2, 3... Indicator, 4... 1st
Switch means, 5... Control valve, 7, 8, 9... Second, third, fourth switch means, 10, 11, 12
...First, second, third addition means, 13, 14...
first and second filter means, 15, 16...first;
Second sequence circuit.

補正昭６３．１０．３図面の簡単な説明を次のように補正する。明細書９頁１７行目、「はその……第４は……
」とあるのを「はその……第４図は……」と補正
する。Amendment October 3, 1981 The brief description of the drawing is amended as follows. Page 9, line 17 of the specification, “The fourth one is...
" is corrected to "That's...Figure 4 is...".

Claims

[Scope of utility model registration request]

a first switch means for switching between the first and second signal sources; a first addition means for adding the output of this switch means and the output of a fourth switch means to be described later to the input of the controller; a second switch means for switching between the output of the first addition means and the output of the first addition means and interlocking with the first switch means; a third switch means interlocked with the third switch means; a second addition means for calculating the difference between the output of the first signal and the second switch means; and a second addition means for calculating the difference between the output of the second signal and the third switch means. a third addition means; first and second primary lag filter means receiving the outputs of the second and third addition means; and switching the outputs of these primary lag filter means and interlocking with the first switch means. fourth switch means, wherein the first-order lag filter element has a time constant controlled to zero when its output is not selected by the fourth switch means. switching circuit.