JPS64331U - - Google Patents

Info

Publication number
JPS64331U
JPS64331U JP9412387U JP9412387U JPS64331U JP S64331 U JPS64331 U JP S64331U JP 9412387 U JP9412387 U JP 9412387U JP 9412387 U JP9412387 U JP 9412387U JP S64331 U JPS64331 U JP S64331U
Authority
JP
Japan
Prior art keywords
elements
utility
scope
registration request
triangular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9412387U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9412387U priority Critical patent/JPS64331U/ja
Publication of JPS64331U publication Critical patent/JPS64331U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
JP9412387U 1987-06-19 1987-06-19 Pending JPS64331U (pt)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9412387U JPS64331U (pt) 1987-06-19 1987-06-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9412387U JPS64331U (pt) 1987-06-19 1987-06-19

Publications (1)

Publication Number Publication Date
JPS64331U true JPS64331U (pt) 1989-01-05

Family

ID=30957279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9412387U Pending JPS64331U (pt) 1987-06-19 1987-06-19

Country Status (1)

Country Link
JP (1) JPS64331U (pt)

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