JPS6431255A - Single chip microcomputer - Google Patents

Single chip microcomputer

Info

Publication number
JPS6431255A
JPS6431255A JP18910587A JP18910587A JPS6431255A JP S6431255 A JPS6431255 A JP S6431255A JP 18910587 A JP18910587 A JP 18910587A JP 18910587 A JP18910587 A JP 18910587A JP S6431255 A JPS6431255 A JP S6431255A
Authority
JP
Japan
Prior art keywords
signal
memory
latch
generating part
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18910587A
Other languages
Japanese (ja)
Other versions
JPH0634240B2 (en
Inventor
Mineo Akashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18910587A priority Critical patent/JPH0634240B2/en
Publication of JPS6431255A publication Critical patent/JPS6431255A/en
Publication of JPH0634240B2 publication Critical patent/JPH0634240B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To suppress the propagation of an abnormal signal after the holding time of a dynamic circuit by adding a circuit for detecting a sampling time and generating a signal longer than the sampling time of a memory to the program memory. CONSTITUTION:A latch signal generating part for latching the output signal of the program memory 4 and a latch circuit 34 are integrated on the base of a single semiconductor, so that the titled microcomputer is constituted. The program memory 4 is precharged and dynamically read synchronously with a signal from a clock generating part 2. Then, the latch signal generating part generates the latch signal of a pulse duration longer than the sampling time of the memory 4 synchronously with a signal from the clock generating part 2 to store and hold the output of the memory 4 of a normal sampling state at that time in the latch circuit 34 and supply to the respective required parts of a device from the latch circuit 34. Thereby, the propagation of the signal of an abnormal value is suppressed and the device can be constantly operated based on a normal signal.
JP18910587A 1987-07-28 1987-07-28 Single-chip micro computer Expired - Lifetime JPH0634240B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18910587A JPH0634240B2 (en) 1987-07-28 1987-07-28 Single-chip micro computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18910587A JPH0634240B2 (en) 1987-07-28 1987-07-28 Single-chip micro computer

Publications (2)

Publication Number Publication Date
JPS6431255A true JPS6431255A (en) 1989-02-01
JPH0634240B2 JPH0634240B2 (en) 1994-05-02

Family

ID=16235447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18910587A Expired - Lifetime JPH0634240B2 (en) 1987-07-28 1987-07-28 Single-chip micro computer

Country Status (1)

Country Link
JP (1) JPH0634240B2 (en)

Also Published As

Publication number Publication date
JPH0634240B2 (en) 1994-05-02

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