JPS6428744A - Scanning system for logical device - Google Patents

Scanning system for logical device

Info

Publication number
JPS6428744A
JPS6428744A JP62183313A JP18331387A JPS6428744A JP S6428744 A JPS6428744 A JP S6428744A JP 62183313 A JP62183313 A JP 62183313A JP 18331387 A JP18331387 A JP 18331387A JP S6428744 A JPS6428744 A JP S6428744A
Authority
JP
Japan
Prior art keywords
address
decoder
scan
devices
logical device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62183313A
Other languages
Japanese (ja)
Inventor
Hiroaki Sato
Toshiyuki Okamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62183313A priority Critical patent/JPS6428744A/en
Publication of JPS6428744A publication Critical patent/JPS6428744A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To quickly and easily set and read the internal state by providing not only a means which scans FFs in a logical device with an address unique in the logical device but also a means which scans them with a common address. CONSTITUTION:For example, plural channel devices 6 are provided in an input/ output processing device and the principal logic part of each device 6 is realized with an LSI. The scan address is set to an address register 11 in a scan control part 10. The set scan address is decoded by a decoder 12, which decodes scan addresses of individual devices 6, and a decoder 13 which decodes the scan address common to all devices 6. All devices are quickly initialized as block multiplexer channels by the output of the decoder 13, and a desired device 6 is quickly initialized as a byte multiplexer channel by the output of the decoder 12.
JP62183313A 1987-07-24 1987-07-24 Scanning system for logical device Pending JPS6428744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62183313A JPS6428744A (en) 1987-07-24 1987-07-24 Scanning system for logical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183313A JPS6428744A (en) 1987-07-24 1987-07-24 Scanning system for logical device

Publications (1)

Publication Number Publication Date
JPS6428744A true JPS6428744A (en) 1989-01-31

Family

ID=16133509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62183313A Pending JPS6428744A (en) 1987-07-24 1987-07-24 Scanning system for logical device

Country Status (1)

Country Link
JP (1) JPS6428744A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2332640A1 (en) 1973-06-27 1975-01-16 Toyo Jozo Kk METHOD FOR MANUFACTURING ENCAPSULATED OR EMBEDDED DRUG

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2332640A1 (en) 1973-06-27 1975-01-16 Toyo Jozo Kk METHOD FOR MANUFACTURING ENCAPSULATED OR EMBEDDED DRUG

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