JPS6426966A - Synchronous communication method for parallel computers - Google Patents

Synchronous communication method for parallel computers

Info

Publication number
JPS6426966A
JPS6426966A JP18395487A JP18395487A JPS6426966A JP S6426966 A JPS6426966 A JP S6426966A JP 18395487 A JP18395487 A JP 18395487A JP 18395487 A JP18395487 A JP 18395487A JP S6426966 A JPS6426966 A JP S6426966A
Authority
JP
Japan
Prior art keywords
register
parallel computers
registers
processing units
synchronous communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18395487A
Other languages
Japanese (ja)
Other versions
JPH07117945B2 (en
Inventor
Kimiharu Okabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18395487A priority Critical patent/JPH07117945B2/en
Publication of JPS6426966A publication Critical patent/JPS6426966A/en
Publication of JPH07117945B2 publication Critical patent/JPH07117945B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To increase the communication speed for synchronous communication among processing units of the parallel computers connected adjacently to each other in an n-dimensional state, by using said processing units and a register contained in a control unit to control packet data. CONSTITUTION:When data communication control is carried out among processing units PU21-2m of the parallel computers connected adjacently to each other in the n-dimensional state, a register 3 is added to a control unit CU together with registers 31-3m set into the units PU21-2m respectively. In case the registers 31-3m defines the 2-dimensional state (X, Y) with 1st and 2nd bits, the register 3 instructs at first the X-directional transmission to the PU21-2m owing to an uncompleted state of transmission. Thus those PUs resets the 1st bit of the register and perform the Y-directional transmission. The registers 31-3m are replaced via an OR operation part 4.
JP18395487A 1987-07-23 1987-07-23 Synchronous communication method in parallel computer Expired - Lifetime JPH07117945B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18395487A JPH07117945B2 (en) 1987-07-23 1987-07-23 Synchronous communication method in parallel computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18395487A JPH07117945B2 (en) 1987-07-23 1987-07-23 Synchronous communication method in parallel computer

Publications (2)

Publication Number Publication Date
JPS6426966A true JPS6426966A (en) 1989-01-30
JPH07117945B2 JPH07117945B2 (en) 1995-12-18

Family

ID=16144721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18395487A Expired - Lifetime JPH07117945B2 (en) 1987-07-23 1987-07-23 Synchronous communication method in parallel computer

Country Status (1)

Country Link
JP (1) JPH07117945B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650330B2 (en) 1999-12-06 2003-11-18 Nvidia Corporation Graphics system and method for processing multiple independent execution threads
US6992667B2 (en) 1999-12-06 2006-01-31 Nvidia Corporation Single semiconductor graphics platform system and method with skinning, swizzling and masking capabilities

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650330B2 (en) 1999-12-06 2003-11-18 Nvidia Corporation Graphics system and method for processing multiple independent execution threads
US6778176B2 (en) 1999-12-06 2004-08-17 Nvidia Corporation Sequencer system and method for sequencing graphics processing
US6992667B2 (en) 1999-12-06 2006-01-31 Nvidia Corporation Single semiconductor graphics platform system and method with skinning, swizzling and masking capabilities

Also Published As

Publication number Publication date
JPH07117945B2 (en) 1995-12-18

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