JPS6425226A - Program start up circuit - Google Patents

Program start up circuit

Info

Publication number
JPS6425226A
JPS6425226A JP62181486A JP18148687A JPS6425226A JP S6425226 A JPS6425226 A JP S6425226A JP 62181486 A JP62181486 A JP 62181486A JP 18148687 A JP18148687 A JP 18148687A JP S6425226 A JPS6425226 A JP S6425226A
Authority
JP
Japan
Prior art keywords
switch
power
output
time
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62181486A
Other languages
Japanese (ja)
Inventor
Nobuo Kameoka
Masato Haraguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62181486A priority Critical patent/JPS6425226A/en
Publication of JPS6425226A publication Critical patent/JPS6425226A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stored Programmes (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To facilitate an input operation, by detecting an ON and an OFF states after the prescribed time of the depression of a non-lock switch, and starting up a program corresponding to the state. CONSTITUTION:In a circuit 18 which outputs a power from a power source input terminal 15 to a power source output terminal 16, the power is supplied to the terminal 16 via a power control transistor 8 by rising a J-KFF7 by depressing the non-lock switch 17. Meanwhile, the AND of the output of an address decoder 10 and an I/O lead wire 13 is outputted to the gate of a data bus buffer 9, and also, the output of the switch 17 is inputted to the buffer 9, and a specific address is read, and the state of the switch 17 at that time is transferred to a data bus 11. in such a way, it is possible to start up plural programs by adjusting the depressing time of the switch 17.
JP62181486A 1987-07-21 1987-07-21 Program start up circuit Pending JPS6425226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181486A JPS6425226A (en) 1987-07-21 1987-07-21 Program start up circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181486A JPS6425226A (en) 1987-07-21 1987-07-21 Program start up circuit

Publications (1)

Publication Number Publication Date
JPS6425226A true JPS6425226A (en) 1989-01-27

Family

ID=16101604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181486A Pending JPS6425226A (en) 1987-07-21 1987-07-21 Program start up circuit

Country Status (1)

Country Link
JP (1) JPS6425226A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696319A (en) * 1979-12-28 1981-08-04 Ricoh Co Ltd Key input device
JPS6158851A (en) * 1984-08-24 1986-03-26 株式会社イナックス Manufacture of artificial marble
JPS6123729B2 (en) * 1980-04-07 1986-06-07 Tokyo Shibaura Electric Co

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696319A (en) * 1979-12-28 1981-08-04 Ricoh Co Ltd Key input device
JPS6123729B2 (en) * 1980-04-07 1986-06-07 Tokyo Shibaura Electric Co
JPS6158851A (en) * 1984-08-24 1986-03-26 株式会社イナックス Manufacture of artificial marble

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